drm/nouveau/bus: convert to new-style nvkm_subdev (bb23f9d7) · Commits · github.com / kvm-riscv / linux

drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h

+8 −34

Original line number	Diff line number	Diff line
		@@ -2,49 +2,23 @@
		#define __NVKM_BUS_H__
		#include <core/subdev.h>

		struct nvkm_bus_intr {
		u32 stat;
		u32 unit;
		};

		struct nvkm_bus {
		const struct nvkm_bus_func *func;
		struct nvkm_subdev subdev;
		int (hwsq_exec)(struct nvkm_bus , u32 *, u32);
		u32 hwsq_size;
		};

		static inline struct nvkm_bus *
		nvkm_bus(void *obj)
		{
		return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_BUS);
		}

		#define nvkm_bus_create(p, e, o, d) \
		nvkm_subdev_create_((p), (e), (o), 0, "PBUS", "master", \
		sizeof(d), (void )d)
		#define nvkm_bus_destroy(p) \
		nvkm_subdev_destroy(&(p)->subdev)
		#define nvkm_bus_init(p) \
		nvkm_subdev_init_old(&(p)->subdev)
		#define nvkm_bus_fini(p, s) \
		nvkm_subdev_fini_old(&(p)->subdev, (s))

		#define _nvkm_bus_dtor _nvkm_subdev_dtor
		#define _nvkm_bus_init _nvkm_subdev_init
		#define _nvkm_bus_fini _nvkm_subdev_fini

		extern struct nvkm_oclass *nv04_bus_oclass;
		extern struct nvkm_oclass *nv31_bus_oclass;
		extern struct nvkm_oclass *nv50_bus_oclass;
		extern struct nvkm_oclass *g94_bus_oclass;
		extern struct nvkm_oclass *gf100_bus_oclass;

		/* interface to sequencer */
		struct nvkm_hwsq;
		int nvkm_hwsq_init(struct nvkm_bus , struct nvkm_hwsq *);
		int nvkm_hwsq_init(struct nvkm_subdev , struct nvkm_hwsq *);
		int nvkm_hwsq_fini(struct nvkm_hwsq **, bool exec);
		void nvkm_hwsq_wr32(struct nvkm_hwsq *, u32 addr, u32 data);
		void nvkm_hwsq_setf(struct nvkm_hwsq *, u8 flag, int data);
		void nvkm_hwsq_wait(struct nvkm_hwsq *, u8 flag, u8 data);
		void nvkm_hwsq_nsec(struct nvkm_hwsq *, u32 nsec);

		int nv04_bus_new(struct nvkm_device , int, struct nvkm_bus *);
		int nv31_bus_new(struct nvkm_device , int, struct nvkm_bus *);
		int nv50_bus_new(struct nvkm_device , int, struct nvkm_bus *);
		int g94_bus_new(struct nvkm_device , int, struct nvkm_bus *);
		int gf100_bus_new(struct nvkm_device , int, struct nvkm_bus *);
		#endif

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

+69 −69

Original line number	Diff line number	Diff line
		@@ -77,7 +77,7 @@ static const struct nvkm_device_chip
		nv4_chipset = {
		.name = "NV04",
		.bios = nvkm_bios_new,
		// .bus = nv04_bus_new,
		.bus = nv04_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv04_devinit_new,
		// .fb = nv04_fb_new,
		@@ -97,7 +97,7 @@ static const struct nvkm_device_chip
		nv5_chipset = {
		.name = "NV05",
		.bios = nvkm_bios_new,
		// .bus = nv04_bus_new,
		.bus = nv04_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv05_devinit_new,
		// .fb = nv04_fb_new,
		@@ -117,7 +117,7 @@ static const struct nvkm_device_chip
		nv10_chipset = {
		.name = "NV10",
		.bios = nvkm_bios_new,
		// .bus = nv04_bus_new,
		.bus = nv04_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv10_devinit_new,
		// .fb = nv10_fb_new,
		@@ -136,7 +136,7 @@ static const struct nvkm_device_chip
		nv11_chipset = {
		.name = "NV11",
		.bios = nvkm_bios_new,
		// .bus = nv04_bus_new,
		.bus = nv04_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv10_devinit_new,
		// .fb = nv10_fb_new,
		@@ -157,7 +157,7 @@ static const struct nvkm_device_chip
		nv15_chipset = {
		.name = "NV15",
		.bios = nvkm_bios_new,
		// .bus = nv04_bus_new,
		.bus = nv04_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv10_devinit_new,
		// .fb = nv10_fb_new,
		@@ -178,7 +178,7 @@ static const struct nvkm_device_chip
		nv17_chipset = {
		.name = "NV17",
		.bios = nvkm_bios_new,
		// .bus = nv04_bus_new,
		.bus = nv04_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv10_devinit_new,
		// .fb = nv10_fb_new,
		@@ -199,7 +199,7 @@ static const struct nvkm_device_chip
		nv18_chipset = {
		.name = "NV18",
		.bios = nvkm_bios_new,
		// .bus = nv04_bus_new,
		.bus = nv04_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv10_devinit_new,
		// .fb = nv10_fb_new,
		@@ -220,7 +220,7 @@ static const struct nvkm_device_chip
		nv1a_chipset = {
		.name = "nForce",
		.bios = nvkm_bios_new,
		// .bus = nv04_bus_new,
		.bus = nv04_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv1a_fb_new,
		@@ -241,7 +241,7 @@ static const struct nvkm_device_chip
		nv1f_chipset = {
		.name = "nForce2",
		.bios = nvkm_bios_new,
		// .bus = nv04_bus_new,
		.bus = nv04_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv1a_fb_new,
		@@ -262,7 +262,7 @@ static const struct nvkm_device_chip
		nv20_chipset = {
		.name = "NV20",
		.bios = nvkm_bios_new,
		// .bus = nv04_bus_new,
		.bus = nv04_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv20_devinit_new,
		// .fb = nv20_fb_new,
		@@ -283,7 +283,7 @@ static const struct nvkm_device_chip
		nv25_chipset = {
		.name = "NV25",
		.bios = nvkm_bios_new,
		// .bus = nv04_bus_new,
		.bus = nv04_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv20_devinit_new,
		// .fb = nv25_fb_new,
		@@ -304,7 +304,7 @@ static const struct nvkm_device_chip
		nv28_chipset = {
		.name = "NV28",
		.bios = nvkm_bios_new,
		// .bus = nv04_bus_new,
		.bus = nv04_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv20_devinit_new,
		// .fb = nv25_fb_new,
		@@ -325,7 +325,7 @@ static const struct nvkm_device_chip
		nv2a_chipset = {
		.name = "NV2A",
		.bios = nvkm_bios_new,
		// .bus = nv04_bus_new,
		.bus = nv04_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv20_devinit_new,
		// .fb = nv25_fb_new,
		@@ -346,7 +346,7 @@ static const struct nvkm_device_chip
		nv30_chipset = {
		.name = "NV30",
		.bios = nvkm_bios_new,
		// .bus = nv04_bus_new,
		.bus = nv04_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv20_devinit_new,
		// .fb = nv30_fb_new,
		@@ -367,7 +367,7 @@ static const struct nvkm_device_chip
		nv31_chipset = {
		.name = "NV31",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv20_devinit_new,
		// .fb = nv30_fb_new,
		@@ -389,7 +389,7 @@ static const struct nvkm_device_chip
		nv34_chipset = {
		.name = "NV34",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv10_devinit_new,
		// .fb = nv10_fb_new,
		@@ -411,7 +411,7 @@ static const struct nvkm_device_chip
		nv35_chipset = {
		.name = "NV35",
		.bios = nvkm_bios_new,
		// .bus = nv04_bus_new,
		.bus = nv04_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv20_devinit_new,
		// .fb = nv35_fb_new,
		@@ -432,7 +432,7 @@ static const struct nvkm_device_chip
		nv36_chipset = {
		.name = "NV36",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv04_clk_new,
		// .devinit = nv20_devinit_new,
		// .fb = nv36_fb_new,
		@@ -454,7 +454,7 @@ static const struct nvkm_device_chip
		nv40_chipset = {
		.name = "NV40",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv40_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv40_fb_new,
		@@ -479,7 +479,7 @@ static const struct nvkm_device_chip
		nv41_chipset = {
		.name = "NV41",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv40_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv41_fb_new,
		@@ -504,7 +504,7 @@ static const struct nvkm_device_chip
		nv42_chipset = {
		.name = "NV42",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv40_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv41_fb_new,
		@@ -529,7 +529,7 @@ static const struct nvkm_device_chip
		nv43_chipset = {
		.name = "NV43",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv40_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv41_fb_new,
		@@ -554,7 +554,7 @@ static const struct nvkm_device_chip
		nv44_chipset = {
		.name = "NV44",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv40_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv44_fb_new,
		@@ -579,7 +579,7 @@ static const struct nvkm_device_chip
		nv45_chipset = {
		.name = "NV45",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv40_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv40_fb_new,
		@@ -604,7 +604,7 @@ static const struct nvkm_device_chip
		nv46_chipset = {
		.name = "G72",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv40_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv46_fb_new,
		@@ -629,7 +629,7 @@ static const struct nvkm_device_chip
		nv47_chipset = {
		.name = "G70",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv40_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv47_fb_new,
		@@ -654,7 +654,7 @@ static const struct nvkm_device_chip
		nv49_chipset = {
		.name = "G71",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv40_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv49_fb_new,
		@@ -679,7 +679,7 @@ static const struct nvkm_device_chip
		nv4a_chipset = {
		.name = "NV44A",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv40_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv44_fb_new,
		@@ -704,7 +704,7 @@ static const struct nvkm_device_chip
		nv4b_chipset = {
		.name = "G73",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv40_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv49_fb_new,
		@@ -729,7 +729,7 @@ static const struct nvkm_device_chip
		nv4c_chipset = {
		.name = "C61",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv40_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv46_fb_new,
		@@ -754,7 +754,7 @@ static const struct nvkm_device_chip
		nv4e_chipset = {
		.name = "C51",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv40_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv4e_fb_new,
		@@ -780,7 +780,7 @@ nv50_chipset = {
		.name = "G80",
		.bar = nv50_bar_new,
		.bios = nvkm_bios_new,
		// .bus = nv50_bus_new,
		.bus = nv50_bus_new,
		// .clk = nv50_clk_new,
		// .devinit = nv50_devinit_new,
		// .fb = nv50_fb_new,
		@@ -807,7 +807,7 @@ static const struct nvkm_device_chip
		nv63_chipset = {
		.name = "C73",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv40_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv46_fb_new,
		@@ -832,7 +832,7 @@ static const struct nvkm_device_chip
		nv67_chipset = {
		.name = "C67",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv40_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv46_fb_new,
		@@ -857,7 +857,7 @@ static const struct nvkm_device_chip
		nv68_chipset = {
		.name = "C68",
		.bios = nvkm_bios_new,
		// .bus = nv31_bus_new,
		.bus = nv31_bus_new,
		// .clk = nv40_clk_new,
		// .devinit = nv1a_devinit_new,
		// .fb = nv46_fb_new,
		@@ -883,7 +883,7 @@ nv84_chipset = {
		.name = "G84",
		.bar = g84_bar_new,
		.bios = nvkm_bios_new,
		// .bus = nv50_bus_new,
		.bus = nv50_bus_new,
		// .clk = g84_clk_new,
		// .devinit = g84_devinit_new,
		// .fb = g84_fb_new,
		@@ -914,7 +914,7 @@ nv86_chipset = {
		.name = "G86",
		.bar = g84_bar_new,
		.bios = nvkm_bios_new,
		// .bus = nv50_bus_new,
		.bus = nv50_bus_new,
		// .clk = g84_clk_new,
		// .devinit = g84_devinit_new,
		// .fb = g84_fb_new,
		@@ -945,7 +945,7 @@ nv92_chipset = {
		.name = "G92",
		.bar = g84_bar_new,
		.bios = nvkm_bios_new,
		// .bus = nv50_bus_new,
		.bus = nv50_bus_new,
		// .clk = g84_clk_new,
		// .devinit = g84_devinit_new,
		// .fb = g84_fb_new,
		@@ -976,7 +976,7 @@ nv94_chipset = {
		.name = "G94",
		.bar = g84_bar_new,
		.bios = nvkm_bios_new,
		// .bus = g94_bus_new,
		.bus = g94_bus_new,
		// .clk = g84_clk_new,
		// .devinit = g84_devinit_new,
		// .fb = g84_fb_new,
		@@ -1014,7 +1014,7 @@ nv96_chipset = {
		// .mxm = nv50_mxm_new,
		// .devinit = g84_devinit_new,
		// .mc = g94_mc_new,
		// .bus = g94_bus_new,
		.bus = g94_bus_new,
		// .timer = nv04_timer_new,
		// .fb = g84_fb_new,
		// .imem = nv50_instmem_new,
		@@ -1045,7 +1045,7 @@ nv98_chipset = {
		// .mxm = nv50_mxm_new,
		// .devinit = g98_devinit_new,
		// .mc = g98_mc_new,
		// .bus = g94_bus_new,
		.bus = g94_bus_new,
		// .timer = nv04_timer_new,
		// .fb = g84_fb_new,
		// .imem = nv50_instmem_new,
		@@ -1069,7 +1069,7 @@ nva0_chipset = {
		.name = "GT200",
		.bar = g84_bar_new,
		.bios = nvkm_bios_new,
		// .bus = g94_bus_new,
		.bus = g94_bus_new,
		// .clk = g84_clk_new,
		// .devinit = g84_devinit_new,
		// .fb = g84_fb_new,
		@@ -1100,7 +1100,7 @@ nva3_chipset = {
		.name = "GT215",
		.bar = g84_bar_new,
		.bios = nvkm_bios_new,
		// .bus = g94_bus_new,
		.bus = g94_bus_new,
		// .clk = gt215_clk_new,
		// .devinit = gt215_devinit_new,
		// .fb = gt215_fb_new,
		@@ -1133,7 +1133,7 @@ nva5_chipset = {
		.name = "GT216",
		.bar = g84_bar_new,
		.bios = nvkm_bios_new,
		// .bus = g94_bus_new,
		.bus = g94_bus_new,
		// .clk = gt215_clk_new,
		// .devinit = gt215_devinit_new,
		// .fb = gt215_fb_new,
		@@ -1165,7 +1165,7 @@ nva8_chipset = {
		.name = "GT218",
		.bar = g84_bar_new,
		.bios = nvkm_bios_new,
		// .bus = g94_bus_new,
		.bus = g94_bus_new,
		// .clk = gt215_clk_new,
		// .devinit = gt215_devinit_new,
		// .fb = gt215_fb_new,
		@@ -1197,7 +1197,7 @@ nvaa_chipset = {
		.name = "MCP77/MCP78",
		.bar = g84_bar_new,
		.bios = nvkm_bios_new,
		// .bus = g94_bus_new,
		.bus = g94_bus_new,
		// .clk = mcp77_clk_new,
		// .devinit = g98_devinit_new,
		// .fb = mcp77_fb_new,
		@@ -1228,7 +1228,7 @@ nvac_chipset = {
		.name = "MCP79/MCP7A",
		.bar = g84_bar_new,
		.bios = nvkm_bios_new,
		// .bus = g94_bus_new,
		.bus = g94_bus_new,
		// .clk = mcp77_clk_new,
		// .devinit = g98_devinit_new,
		// .fb = mcp77_fb_new,
		@@ -1259,7 +1259,7 @@ nvaf_chipset = {
		.name = "MCP89",
		.bar = g84_bar_new,
		.bios = nvkm_bios_new,
		// .bus = g94_bus_new,
		.bus = g94_bus_new,
		// .clk = gt215_clk_new,
		// .devinit = mcp89_devinit_new,
		// .fb = mcp89_fb_new,
		@@ -1291,7 +1291,7 @@ nvc0_chipset = {
		.name = "GF100",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gf100_clk_new,
		// .devinit = gf100_devinit_new,
		// .fb = gf100_fb_new,
		@@ -1326,7 +1326,7 @@ nvc1_chipset = {
		.name = "GF108",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gf100_clk_new,
		// .devinit = gf100_devinit_new,
		// .fb = gf100_fb_new,
		@@ -1360,7 +1360,7 @@ nvc3_chipset = {
		.name = "GF106",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gf100_clk_new,
		// .devinit = gf100_devinit_new,
		// .fb = gf100_fb_new,
		@@ -1394,7 +1394,7 @@ nvc4_chipset = {
		.name = "GF104",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gf100_clk_new,
		// .devinit = gf100_devinit_new,
		// .fb = gf100_fb_new,
		@@ -1429,7 +1429,7 @@ nvc8_chipset = {
		.name = "GF110",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gf100_clk_new,
		// .devinit = gf100_devinit_new,
		// .fb = gf100_fb_new,
		@@ -1464,7 +1464,7 @@ nvce_chipset = {
		.name = "GF114",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gf100_clk_new,
		// .devinit = gf100_devinit_new,
		// .fb = gf100_fb_new,
		@@ -1499,7 +1499,7 @@ nvcf_chipset = {
		.name = "GF116",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gf100_clk_new,
		// .devinit = gf100_devinit_new,
		// .fb = gf100_fb_new,
		@@ -1533,7 +1533,7 @@ nvd7_chipset = {
		.name = "GF117",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gf100_clk_new,
		// .devinit = gf100_devinit_new,
		// .fb = gf100_fb_new,
		@@ -1565,7 +1565,7 @@ nvd9_chipset = {
		.name = "GF119",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gf100_clk_new,
		// .devinit = gf100_devinit_new,
		// .fb = gf100_fb_new,
		@@ -1599,7 +1599,7 @@ nve4_chipset = {
		.name = "GK104",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gk104_clk_new,
		// .devinit = gf100_devinit_new,
		// .fb = gk104_fb_new,
		@@ -1635,7 +1635,7 @@ nve6_chipset = {
		.name = "GK106",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gk104_clk_new,
		// .devinit = gf100_devinit_new,
		// .fb = gk104_fb_new,
		@@ -1671,7 +1671,7 @@ nve7_chipset = {
		.name = "GK107",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gk104_clk_new,
		// .devinit = gf100_devinit_new,
		// .fb = gk104_fb_new,
		@@ -1706,7 +1706,7 @@ static const struct nvkm_device_chip
		nvea_chipset = {
		.name = "GK20A",
		.bar = gk20a_bar_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gk20a_clk_new,
		// .fb = gk20a_fb_new,
		// .fuse = gf100_fuse_new,
		@@ -1731,7 +1731,7 @@ nvf0_chipset = {
		.name = "GK110",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gk104_clk_new,
		// .devinit = gf100_devinit_new,
		// .fb = gk104_fb_new,
		@@ -1767,7 +1767,7 @@ nvf1_chipset = {
		.name = "GK110B",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gk104_clk_new,
		// .devinit = gf100_devinit_new,
		// .fb = gk104_fb_new,
		@@ -1803,7 +1803,7 @@ nv106_chipset = {
		.name = "GK208B",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gk104_clk_new,
		// .devinit = gf100_devinit_new,
		// .fb = gk104_fb_new,
		@@ -1838,7 +1838,7 @@ nv108_chipset = {
		.name = "GK208",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gk104_clk_new,
		// .devinit = gf100_devinit_new,
		// .fb = gk104_fb_new,
		@@ -1873,7 +1873,7 @@ nv117_chipset = {
		.name = "GM107",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .clk = gk104_clk_new,
		// .devinit = gm107_devinit_new,
		// .fb = gm107_fb_new,
		@@ -1903,7 +1903,7 @@ nv124_chipset = {
		.name = "GM204",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .devinit = gm204_devinit_new,
		// .fb = gm107_fb_new,
		// .fuse = gm107_fuse_new,
		@@ -1932,7 +1932,7 @@ nv126_chipset = {
		.name = "GM206",
		.bar = gf100_bar_new,
		.bios = nvkm_bios_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .devinit = gm204_devinit_new,
		// .fb = gm107_fb_new,
		// .fuse = gm107_fuse_new,
		@@ -1960,7 +1960,7 @@ static const struct nvkm_device_chip
		nv12b_chipset = {
		.name = "GM20B",
		.bar = gk20a_bar_new,
		// .bus = gf100_bus_new,
		.bus = gf100_bus_new,
		// .fb = gk20a_fb_new,
		// .fuse = gm107_fuse_new,
		// .ibus = gk20a_ibus_new,

drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c

+0 −9

Original line number	Diff line number	Diff line
		@@ -36,7 +36,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
		@@ -66,7 +65,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
		@@ -96,7 +94,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
		@@ -125,7 +122,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
		@@ -155,7 +151,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
		@@ -184,7 +179,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
		@@ -213,7 +207,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
		@@ -243,7 +236,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
		@@ -272,7 +264,6 @@ gf100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c

+0 −8

Original line number	Diff line number	Diff line
		@@ -36,7 +36,6 @@ gk104_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
		@@ -67,7 +66,6 @@ gk104_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
		@@ -98,7 +96,6 @@ gk104_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
		@@ -123,7 +120,6 @@ gk104_identify(struct nvkm_device *device)
		case 0xea:
		device->oclass[NVDEV_SUBDEV_CLK ] = &gk20a_clk_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass;
		@@ -149,7 +145,6 @@ gk104_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
		@@ -180,7 +175,6 @@ gk104_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
		@@ -211,7 +205,6 @@ gk104_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
		@@ -241,7 +234,6 @@ gk104_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c

+0 −4

Original line number	Diff line number	Diff line
		@@ -36,7 +36,6 @@ gm100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
		@@ -77,7 +76,6 @@ gm100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
		@@ -115,7 +113,6 @@ gm100_identify(struct nvkm_device *device)
		device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
		@@ -144,7 +141,6 @@ gm100_identify(struct nvkm_device *device)

		device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
		device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass;