Commit bb0f8429 authored by Mario Limonciello's avatar Mario Limonciello Committed by Alex Deucher
Browse files

drm/amd: Move seamless boot check out of display 



This will allow base driver to dictate whether seamless should be
enabled.  No intended functional changes.

Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3ef07651

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −0
Original line number Diff line number Diff line
@@ -1326,6 +1326,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 
void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);

int amdgpu_device_pci_reset(struct amdgpu_device *adev);

bool amdgpu_device_need_post(struct amdgpu_device *adev);

bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev);

bool amdgpu_device_pcie_dynamic_switching_supported(void);

bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);

bool amdgpu_device_aspm_support_quirk(void);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+21 −0
Original line number Diff line number Diff line
@@ -1358,6 +1358,27 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev) 
	return true;

}



/*

 * Check whether seamless boot is supported.

 *

 * So far we only support seamless boot on select ASICs.

 * If everything goes well, we may consider expanding

 * seamless boot to other ASICs.

 */

bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev)

{

	switch (adev->ip_versions[DCE_HWIP][0]) {

	case IP_VERSION(3, 0, 1):

		if (!adev->mman.keep_stolen_vga_memory)

			return true;

		break;

	default:

		break;

	}



	return false;

}



/*

 * Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic

 * speed switching. Until we have confirmation from Intel that a specific host

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+1 −22
Original line number Diff line number Diff line
@@ -1680,7 +1680,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) 


	init_data.flags.seamless_boot_edp_requested = false;



	if (check_seamless_boot_capability(adev)) {

	if (amdgpu_device_seamless_boot_supported(adev)) {

		init_data.flags.seamless_boot_edp_requested = true;

		init_data.flags.allow_seamless_boot_optimization = true;

		DRM_INFO("Seamless boot condition check passed\n");
@@ -10993,27 +10993,6 @@ int amdgpu_dm_process_dmub_set_config_sync( 
	return ret;

}



/*

 * Check whether seamless boot is supported.

 *

 * So far we only support seamless boot on CHIP_VANGOGH.

 * If everything goes well, we may consider expanding

 * seamless boot to other ASICs.

 */

bool check_seamless_boot_capability(struct amdgpu_device *adev)

{

	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {

	case IP_VERSION(3, 0, 1):

		if (!adev->mman.keep_stolen_vga_memory)

			return true;

		break;

	default:

		break;

	}



	return false;

}



bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)

{

	return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

+0 −2
Original line number Diff line number Diff line
@@ -825,8 +825,6 @@ int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned in 
int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index,

					struct set_config_cmd_payload *payload, enum set_config_status *operation_result);



bool check_seamless_boot_capability(struct amdgpu_device *adev);



struct dc_stream_state *

	create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,

					const struct drm_display_mode *drm_mode,