Commit bae26849 authored by Vidya Sagar's avatar Vidya Sagar Committed by Bjorn Helgaas
Browse files

PCI/PM: Move pci_dev_wait() definition earlier 

Move the definition of pci_dev_wait() above pci_power_up() so that it can
be called from the latter with no change in functionality.  This is a pure
code move with no functional change.

Link: https://lore.kernel.org/r/20191120051743.23124-1-vidyas@nvidia.com


Signed-off-by: default avatarVidya Sagar <vidyas@nvidia.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent ad9001f2

drivers/pci/pci.c

+41 −41
Original line number Diff line number Diff line
@@ -1012,6 +1012,47 @@ void pci_wakeup_bus(struct pci_bus *bus) 
		pci_walk_bus(bus, pci_wakeup, NULL);

}



static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)

{

	int delay = 1;

	u32 id;



	/*

	 * After reset, the device should not silently discard config

	 * requests, but it may still indicate that it needs more time by

	 * responding to them with CRS completions.  The Root Port will

	 * generally synthesize ~0 data to complete the read (except when

	 * CRS SV is enabled and the read was for the Vendor ID; in that

	 * case it synthesizes 0x0001 data).

	 *

	 * Wait for the device to return a non-CRS completion.  Read the

	 * Command register instead of Vendor ID so we don't have to

	 * contend with the CRS SV value.

	 */

	pci_read_config_dword(dev, PCI_COMMAND, &id);

	while (id == ~0) {

		if (delay > timeout) {

			pci_warn(dev, "not ready %dms after %s; giving up\n",

				 delay - 1, reset_type);

			return -ENOTTY;

		}



		if (delay > 1000)

			pci_info(dev, "not ready %dms after %s; waiting\n",

				 delay - 1, reset_type);



		msleep(delay);

		delay *= 2;

		pci_read_config_dword(dev, PCI_COMMAND, &id);

	}



	if (delay > 1000)

		pci_info(dev, "ready %dms after %s\n", delay - 1,

			 reset_type);



	return 0;

}



/**

 * pci_power_up - Put the given device into D0

 * @dev: PCI device to power up
@@ -4406,47 +4447,6 @@ int pci_wait_for_pending_transaction(struct pci_dev *dev) 
}

EXPORT_SYMBOL(pci_wait_for_pending_transaction);



static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)

{

	int delay = 1;

	u32 id;



	/*

	 * After reset, the device should not silently discard config

	 * requests, but it may still indicate that it needs more time by

	 * responding to them with CRS completions.  The Root Port will

	 * generally synthesize ~0 data to complete the read (except when

	 * CRS SV is enabled and the read was for the Vendor ID; in that

	 * case it synthesizes 0x0001 data).

	 *

	 * Wait for the device to return a non-CRS completion.  Read the

	 * Command register instead of Vendor ID so we don't have to

	 * contend with the CRS SV value.

	 */

	pci_read_config_dword(dev, PCI_COMMAND, &id);

	while (id == ~0) {

		if (delay > timeout) {

			pci_warn(dev, "not ready %dms after %s; giving up\n",

				 delay - 1, reset_type);

			return -ENOTTY;

		}



		if (delay > 1000)

			pci_info(dev, "not ready %dms after %s; waiting\n",

				 delay - 1, reset_type);



		msleep(delay);

		delay *= 2;

		pci_read_config_dword(dev, PCI_COMMAND, &id);

	}



	if (delay > 1000)

		pci_info(dev, "ready %dms after %s\n", delay - 1,

			 reset_type);



	return 0;

}



/**

 * pcie_has_flr - check if a device supports function level resets

 * @dev: device to check