Commit ba7e87c5 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/cadence' 

  - Refactor Cadence PCIe host controller to use as a library for both host
    and endpoint (Tom Joseph)

* remotes/lorenzo/pci/cadence:
  PCI: cadence: Move all files to per-device cadence directory
  PCI: cadence: Refactor driver to use as a core library
parents 318ed91f de80f95c

drivers/pci/controller/Kconfig

+1 −28
Original line number Diff line number Diff line
@@ -22,34 +22,6 @@ config PCI_AARDVARK 
	 controller is part of the South Bridge of the Marvel Armada

	 3700 SoC.



menu "Cadence PCIe controllers support"



config PCIE_CADENCE

	bool



config PCIE_CADENCE_HOST

	bool "Cadence PCIe host controller"

	depends on OF

	depends on PCI

	select IRQ_DOMAIN

	select PCIE_CADENCE

	help

	  Say Y here if you want to support the Cadence PCIe controller in host

	  mode. This PCIe controller may be embedded into many different vendors

	  SoCs.



config PCIE_CADENCE_EP

	bool "Cadence PCIe endpoint controller"

	depends on OF

	depends on PCI_ENDPOINT

	select PCIE_CADENCE

	help

	  Say Y here if you want to support the Cadence PCIe  controller in

	  endpoint mode. This PCIe controller may be embedded into many

	  different vendors SoCs.



endmenu



config PCIE_XILINX_NWL

	bool "NWL PCIe Core"

	depends on ARCH_ZYNQMP || COMPILE_TEST
@@ -289,4 +261,5 @@ config PCI_HYPERV_INTERFACE 
	  have a common interface with the Hyper-V PCI frontend driver.



source "drivers/pci/controller/dwc/Kconfig"

source "drivers/pci/controller/cadence/Kconfig"

endmenu

drivers/pci/controller/Makefile

+1 −3
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o

obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o

obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o

obj-$(CONFIG_PCIE_CADENCE) += cadence/

obj-$(CONFIG_PCI_FTPCI100) += pci-ftpci100.o

obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o

obj-$(CONFIG_PCI_HYPERV_INTERFACE) += pci-hyperv-intf.o

drivers/pci/controller/cadence/Kconfig

0 → 100644
+45 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0



menu "Cadence PCIe controllers support"

	depends on PCI



config PCIE_CADENCE

	bool



config PCIE_CADENCE_HOST

	bool

	depends on OF

	select IRQ_DOMAIN

	select PCIE_CADENCE



config PCIE_CADENCE_EP

	bool

	depends on OF

	depends on PCI_ENDPOINT

	select PCIE_CADENCE



config PCIE_CADENCE_PLAT

	bool



config PCIE_CADENCE_PLAT_HOST

	bool "Cadence PCIe platform host controller"

	depends on OF

	select PCIE_CADENCE_HOST

	select PCIE_CADENCE_PLAT

	help

	  Say Y here if you want to support the Cadence PCIe platform controller in

	  host mode. This PCIe controller may be embedded into many different

	  vendors SoCs.



config PCIE_CADENCE_PLAT_EP

	bool "Cadence PCIe platform endpoint controller"

	depends on OF

	depends on PCI_ENDPOINT

	select PCIE_CADENCE_EP

	select PCIE_CADENCE_PLAT

	help

	  Say Y here if you want to support the Cadence PCIe  platform controller in

	  endpoint mode. This PCIe controller may be embedded into many

	  different vendors SoCs.



endmenu

drivers/pci/controller/cadence/Makefile

0 → 100644
+5 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o

obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o

obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o

obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o

drivers/pci/controller/pcie-cadence-ep.c→drivers/pci/controller/cadence/pcie-cadence-ep.c

+5 −91
Original line number Diff line number Diff line
@@ -17,35 +17,6 @@ 
#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE		0x1

#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY	0x3



/**

 * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver

 * @pcie: Cadence PCIe controller

 * @max_regions: maximum number of regions supported by hardware

 * @ob_region_map: bitmask of mapped outbound regions

 * @ob_addr: base addresses in the AXI bus where the outbound regions start

 * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ

 *		   dedicated outbound regions is mapped.

 * @irq_cpu_addr: base address in the CPU space where a write access triggers

 *		  the sending of a memory write (MSI) / normal message (legacy

 *		  IRQ) TLP through the PCIe bus.

 * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ

 *		  dedicated outbound region.

 * @irq_pci_fn: the latest PCI function that has updated the mapping of

 *		the MSI/legacy IRQ dedicated outbound region.

 * @irq_pending: bitmask of asserted legacy IRQs.

 */

struct cdns_pcie_ep {

	struct cdns_pcie		pcie;

	u32				max_regions;

	unsigned long			ob_region_map;

	phys_addr_t			*ob_addr;

	phys_addr_t			irq_phys_addr;

	void __iomem			*irq_cpu_addr;

	u64				irq_pci_addr;

	u8				irq_pci_fn;

	u8				irq_pending;

};



static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn,

				     struct pci_epf_header *hdr)

{
@@ -424,28 +395,17 @@ static const struct pci_epc_ops cdns_pcie_epc_ops = { 
	.get_features	= cdns_pcie_ep_get_features,

};



static const struct of_device_id cdns_pcie_ep_of_match[] = {

	{ .compatible = "cdns,cdns-pcie-ep" },



	{ },

};



static int cdns_pcie_ep_probe(struct platform_device *pdev)

int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)

{

	struct device *dev = &pdev->dev;

	struct device *dev = ep->pcie.dev;

	struct platform_device *pdev = to_platform_device(dev);

	struct device_node *np = dev->of_node;

	struct cdns_pcie_ep *ep;

	struct cdns_pcie *pcie;

	struct pci_epc *epc;

	struct cdns_pcie *pcie = &ep->pcie;

	struct resource *res;

	struct pci_epc *epc;

	int ret;

	int phy_count;



	ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);

	if (!ep)

		return -ENOMEM;



	pcie = &ep->pcie;

	pcie->is_rc = false;



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
@@ -474,19 +434,6 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev) 
	if (!ep->ob_addr)

		return -ENOMEM;



	ret = cdns_pcie_init_phy(dev, pcie);

	if (ret) {

		dev_err(dev, "failed to init phy\n");

		return ret;

	}

	platform_set_drvdata(pdev, pcie);

	pm_runtime_enable(dev);

	ret = pm_runtime_get_sync(dev);

	if (ret < 0) {

		dev_err(dev, "pm_runtime_get_sync() failed\n");

		goto err_get_sync;

	}



	/* Disable all but function 0 (anyway BIT(0) is hardwired to 1). */

	cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0));
@@ -528,38 +475,5 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev) 
 err_init:

	pm_runtime_put_sync(dev);



 err_get_sync:

	pm_runtime_disable(dev);

	cdns_pcie_disable_phy(pcie);

	phy_count = pcie->phy_count;

	while (phy_count--)

		device_link_del(pcie->link[phy_count]);



	return ret;

}
 


static void cdns_pcie_ep_shutdown(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct cdns_pcie *pcie = dev_get_drvdata(dev);

	int ret;



	ret = pm_runtime_put_sync(dev);

	if (ret < 0)

		dev_dbg(dev, "pm_runtime_put_sync failed\n");



	pm_runtime_disable(dev);



	cdns_pcie_disable_phy(pcie);

}



static struct platform_driver cdns_pcie_ep_driver = {

	.driver = {

		.name = "cdns-pcie-ep",

		.of_match_table = cdns_pcie_ep_of_match,

		.pm	= &cdns_pcie_pm_ops,

	},

	.probe = cdns_pcie_ep_probe,

	.shutdown = cdns_pcie_ep_shutdown,

};

builtin_platform_driver(cdns_pcie_ep_driver);