Commit ba01cf0e authored May 17, 2016 by Paul Burton Committed by Ralf Baechle May 28, 2016

irqchip: mips-gic: Setup EIC mode on each CPU if it's in use



When EIC mode is in use (cpu_has_veic is true) enable it on each CPU
during GIC initialisation. Otherwise there may be a mismatch between the
hardware default interrupt model & that expected by the kernel.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Matt Redfearn <matt.redfearn@imgtec.com>
Tested-by: Matt Redfearn <matt.redfearn@imgtec.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13274/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent d642e4e7

drivers/irqchip/irq-mips-gic.c

+9 −1

Original line number	Diff line number	Diff line
		@@ -968,7 +968,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
		unsigned int cpu_vec, unsigned int irqbase,
		struct device_node *node)
		{
		unsigned int gicconfig;
		unsigned int gicconfig, cpu;
		unsigned int v[2];

		__gic_base_addr = gic_base_addr;
		@@ -985,6 +985,14 @@ static void __init __gic_init(unsigned long gic_base_addr,
		gic_vpes = gic_vpes + 1;

		if (cpu_has_veic) {
		/* Set EIC mode for all VPEs */
		for_each_present_cpu(cpu) {
		gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR),
		mips_cm_vp_id(cpu));
		gic_write(GIC_REG(VPE_OTHER, GIC_VPE_CTL),
		GIC_VPE_CTL_EIC_MODE_MSK);
		}

		/* Always use vector 1 in EIC mode */
		gic_cpu_pin = 0;
		timer_cpu_pin = gic_cpu_pin;