Commit b73bdc50 authored by Serge Semin's avatar Serge Semin Committed by Bjorn Helgaas
Browse files

dmaengine: dw-edma: Use non-atomic io-64 methods 



Instead of splitting 64-bits IOs up into two 32-bits ones, use the existing
non-atomic readq()/writeq() functions. By doing so we can discard
CONFIG_64BIT #ifdefs from the code.

Tested-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: default avatarVinod Koul <vkoul@kernel.org>
parent 5fdca4a9

drivers/dma/dw-edma/dw-edma-v0-core.c

+6 −26
Original line number Diff line number Diff line
@@ -8,6 +8,8 @@ 


#include <linux/bitfield.h>



#include <linux/io-64-nonatomic-lo-hi.h>



#include "dw-edma-core.h"

#include "dw-edma-v0-core.h"

#include "dw-edma-v0-regs.h"
@@ -53,8 +55,6 @@ static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) 
		SET_32(dw, rd_##name, value);		\

	} while (0)



#ifdef CONFIG_64BIT



#define SET_64(dw, name, value)				\

	writeq(value, &(__dw_regs(dw)->name))
@@ -80,8 +80,6 @@ static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) 
		SET_64(dw, rd_##name, value);		\

	} while (0)



#endif /* CONFIG_64BIT */



#define SET_COMPAT(dw, name, value)			\

	writel(value, &(__dw_regs(dw)->type.unroll.name))
@@ -164,8 +162,6 @@ static inline u32 readl_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch, 
#define SET_LL_32(ll, value) \

	writel(value, ll)



#ifdef CONFIG_64BIT



static inline void writeq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,

			     u64 value, void __iomem *addr)

{
@@ -225,8 +221,6 @@ static inline u64 readq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch, 
#define SET_LL_64(ll, value) \

	writeq(value, ll)



#endif /* CONFIG_64BIT */



/* eDMA management callbacks */

void dw_edma_v0_core_off(struct dw_edma *dw)

{
@@ -325,19 +319,10 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) 
		/* Transfer size */

		SET_LL_32(&lli[i].transfer_size, child->sz);

		/* SAR */

		#ifdef CONFIG_64BIT

		SET_LL_64(&lli[i].sar.reg, child->sar);

		#else /* CONFIG_64BIT */

			SET_LL_32(&lli[i].sar.lsb, lower_32_bits(child->sar));

			SET_LL_32(&lli[i].sar.msb, upper_32_bits(child->sar));

		#endif /* CONFIG_64BIT */

		/* DAR */

		#ifdef CONFIG_64BIT

		SET_LL_64(&lli[i].dar.reg, child->dar);

		#else /* CONFIG_64BIT */

			SET_LL_32(&lli[i].dar.lsb, lower_32_bits(child->dar));

			SET_LL_32(&lli[i].dar.msb, upper_32_bits(child->dar));

		#endif /* CONFIG_64BIT */



		i++;

	}
@@ -349,12 +334,7 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) 
	/* Channel control */

	SET_LL_32(&llp->control, control);

	/* Linked list */

	#ifdef CONFIG_64BIT

	SET_LL_64(&llp->llp.reg, chunk->ll_region.paddr);

	#else /* CONFIG_64BIT */

		SET_LL_32(&llp->llp.lsb, lower_32_bits(chunk->ll_region.paddr));

		SET_LL_32(&llp->llp.msb, upper_32_bits(chunk->ll_region.paddr));

	#endif /* CONFIG_64BIT */

}



void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)