Commit b45589b8 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: add mmhub error status query callback for aldebaran 



The callback will be invoked to query mmea error
status when needed.

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarDennis <Li&lt;Dennis.Li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 27ad2ca6

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

+27 −0
Original line number Diff line number Diff line
@@ -1242,6 +1242,32 @@ static void mmhub_v1_7_reset_ras_error_count(struct amdgpu_device *adev) 
	}

}



static const struct soc15_reg_entry mmhub_v1_7_err_status_regs[] = {

	{ SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_ERR_STATUS), 0, 0, 0 },

	{ SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_ERR_STATUS), 0, 0, 0 },

	{ SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_ERR_STATUS), 0, 0, 0 },

	{ SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_ERR_STATUS), 0, 0, 0 },

	{ SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_ERR_STATUS), 0, 0, 0 },

	{ SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_ERR_STATUS), 0, 0, 0 },

};



static void mmhub_v1_7_query_ras_error_status(struct amdgpu_device *adev)

{

	int i;

	uint32_t reg_value;



	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB))

		return;



	for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_err_status_regs); i++) {

		reg_value =

			RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_err_status_regs[i]));

		if (reg_value)

			dev_warn(adev->dev, "MMHUB EA err detected at instance: %d, status: 0x%x!\n",

					i, reg_value);

	}

}



const struct amdgpu_mmhub_funcs mmhub_v1_7_funcs = {

	.ras_late_init = amdgpu_mmhub_ras_late_init,

	.query_ras_error_count = mmhub_v1_7_query_ras_error_count,
@@ -1254,4 +1280,5 @@ const struct amdgpu_mmhub_funcs mmhub_v1_7_funcs = { 
	.set_clockgating = mmhub_v1_7_set_clockgating,

	.get_clockgating = mmhub_v1_7_get_clockgating,

	.setup_vm_pt_regs = mmhub_v1_7_setup_vm_pt_regs,

	.query_ras_error_status = mmhub_v1_7_query_ras_error_status,

};