Loading arch/arm/mach-pxa/include/mach/pxa-regs.h +0 −7 Original line number Diff line number Diff line Loading @@ -553,11 +553,4 @@ * Core Clock - see arch/arm/mach-pxa/include/mach/pxa2xx-regs.h */ /* PWRMODE register M field values */ #define PWRMODE_IDLE 0x1 #define PWRMODE_STANDBY 0x2 #define PWRMODE_SLEEP 0x3 #define PWRMODE_DEEPSLEEP 0x7 #endif arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +7 −0 Original line number Diff line number Diff line Loading @@ -243,4 +243,11 @@ #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ /* PWRMODE register M field values */ #define PWRMODE_IDLE 0x1 #define PWRMODE_STANDBY 0x2 #define PWRMODE_SLEEP 0x3 #define PWRMODE_DEEPSLEEP 0x7 #endif Loading
arch/arm/mach-pxa/include/mach/pxa-regs.h +0 −7 Original line number Diff line number Diff line Loading @@ -553,11 +553,4 @@ * Core Clock - see arch/arm/mach-pxa/include/mach/pxa2xx-regs.h */ /* PWRMODE register M field values */ #define PWRMODE_IDLE 0x1 #define PWRMODE_STANDBY 0x2 #define PWRMODE_SLEEP 0x3 #define PWRMODE_DEEPSLEEP 0x7 #endif
arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +7 −0 Original line number Diff line number Diff line Loading @@ -243,4 +243,11 @@ #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ /* PWRMODE register M field values */ #define PWRMODE_IDLE 0x1 #define PWRMODE_STANDBY 0x2 #define PWRMODE_SLEEP 0x3 #define PWRMODE_DEEPSLEEP 0x7 #endif