Commit b2d91953 authored by Tomer Maimon's avatar Tomer Maimon Committed by Arnd Bergmann
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ARM: dts: add Nuvoton NPCM730 device tree 



Add Nuvoton NPCM730 SoC device tree.

The Nuvoton NPCN730 SoC is a part of the
Nuvoton NPCM7xx SoCs family.

Signed-off-by: default avatarTomer Maimon <tmaimon77@gmail.com>
Reviewed-by: default avatarBenjamin Fair <benjaminfair@google.com>
Link: https://lore.kernel.org/r/20201119080002.100342-1-tmaimon77@gmail.com

'
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 1e548b67

arch/arm/boot/dts/nuvoton-npcm730.dtsi

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// SPDX-License-Identifier: GPL-2.0

// Copyright (c) 2020 Nuvoton Technology



#include "nuvoton-common-npcm7xx.dtsi"



/ {

	#address-cells = <1>;

	#size-cells = <1>;

	interrupt-parent = <&gic>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "nuvoton,npcm750-smp";



		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			clocks = <&clk NPCM7XX_CLK_CPU>;

			clock-names = "clk_cpu";

			reg = <0>;

			next-level-cache = <&l2>;

		};



		cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			clocks = <&clk NPCM7XX_CLK_CPU>;

			clock-names = "clk_cpu";

			reg = <1>;

			next-level-cache = <&l2>;

		};

	};



	soc {

		timer@3fe600 {

			compatible = "arm,cortex-a9-twd-timer";

			reg = <0x3fe600 0x20>;

			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |

						  IRQ_TYPE_LEVEL_HIGH)>;

			clocks = <&clk NPCM7XX_CLK_AHB>;

		};

	};

};