Commit b2d17df3 authored by Srujana Challa's avatar Srujana Challa Committed by Herbert Xu
Browse files

crypto: octeontx2 - add support for OcteonTX2 98xx CPT block. 



OcteonTX2 series of silicons have multiple variants, the
98xx variant has two crypto (CPT0 & CPT1) blocks. This patch
adds support for firmware load on new CPT block(CPT1).

Signed-off-by: default avatarSrujana Challa <schalla@marvell.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 66810912

drivers/crypto/marvell/octeontx2/otx2_cpt_common.h

+5 −5
Original line number Diff line number Diff line
@@ -121,14 +121,14 @@ int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev); 


int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox,

				  struct pci_dev *pdev);

int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox,

			     struct pci_dev *pdev, u64 reg, u64 *val);

int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,

			     u64 reg, u64 *val, int blkaddr);

int otx2_cpt_add_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,

			      u64 reg, u64 val);

			      u64 reg, u64 val, int blkaddr);

int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,

			 u64 reg, u64 *val);

			 u64 reg, u64 *val, int blkaddr);

int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,

			  u64 reg, u64 val);

			  u64 reg, u64 val, int blkaddr);

struct otx2_cptlfs_info;

int otx2_cpt_attach_rscrs_msg(struct otx2_cptlfs_info *lfs);

int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs);

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

+8 −6
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox, struct pci_dev *pdev) 
}



int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,

			     u64 reg, u64 *val)

			     u64 reg, u64 *val, int blkaddr)

{

	struct cpt_rd_wr_reg_msg *reg_msg;
@@ -62,12 +62,13 @@ int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev, 
	reg_msg->is_write = 0;

	reg_msg->reg_offset = reg;

	reg_msg->ret_val = val;

	reg_msg->blkaddr = blkaddr;



	return 0;

}



int otx2_cpt_add_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,

			      u64 reg, u64 val)

			      u64 reg, u64 val, int blkaddr)

{

	struct cpt_rd_wr_reg_msg *reg_msg;
@@ -86,16 +87,17 @@ int otx2_cpt_add_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev, 
	reg_msg->is_write = 1;

	reg_msg->reg_offset = reg;

	reg_msg->val = val;

	reg_msg->blkaddr = blkaddr;



	return 0;

}



int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,

			 u64 reg, u64 *val)

			 u64 reg, u64 *val, int blkaddr)

{

	int ret;



	ret = otx2_cpt_add_read_af_reg(mbox, pdev, reg, val);

	ret = otx2_cpt_add_read_af_reg(mbox, pdev, reg, val, blkaddr);

	if (ret)

		return ret;
@@ -103,11 +105,11 @@ int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev, 
}



int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,

			  u64 reg, u64 val)

			  u64 reg, u64 val, int blkaddr)

{

	int ret;



	ret = otx2_cpt_add_write_af_reg(mbox, pdev, reg, val);

	ret = otx2_cpt_add_write_af_reg(mbox, pdev, reg, val, blkaddr);

	if (ret)

		return ret;

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

+4 −4
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ static int cptlf_set_pri(struct otx2_cptlf_info *lf, int pri) 


	ret = otx2_cpt_read_af_reg(lfs->mbox, lfs->pdev,

				   CPT_AF_LFX_CTL(lf->slot),

				   &lf_ctrl.u);

				   &lf_ctrl.u, lfs->blkaddr);

	if (ret)

		return ret;
@@ -64,7 +64,7 @@ static int cptlf_set_pri(struct otx2_cptlf_info *lf, int pri) 


	ret = otx2_cpt_write_af_reg(lfs->mbox, lfs->pdev,

				    CPT_AF_LFX_CTL(lf->slot),

				    lf_ctrl.u);

				    lf_ctrl.u, lfs->blkaddr);

	return ret;

}
@@ -77,7 +77,7 @@ static int cptlf_set_eng_grps_mask(struct otx2_cptlf_info *lf, 


	ret = otx2_cpt_read_af_reg(lfs->mbox, lfs->pdev,

				   CPT_AF_LFX_CTL(lf->slot),

				   &lf_ctrl.u);

				   &lf_ctrl.u, lfs->blkaddr);

	if (ret)

		return ret;
@@ -85,7 +85,7 @@ static int cptlf_set_eng_grps_mask(struct otx2_cptlf_info *lf, 


	ret = otx2_cpt_write_af_reg(lfs->mbox, lfs->pdev,

				    CPT_AF_LFX_CTL(lf->slot),

				    lf_ctrl.u);

				    lf_ctrl.u, lfs->blkaddr);

	return ret;

}

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

+1 −0
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ struct otx2_cptlfs_info { 
	u8 kcrypto_eng_grp_num;	/* Kernel crypto engine group number */

	u8 kvf_limits;          /* Kernel crypto limits */

	atomic_t state;         /* LF's state. started/reset */

	int blkaddr;            /* CPT blkaddr: BLKADDR_CPT0/BLKADDR_CPT1 */

};



static inline void otx2_cpt_free_instruction_queues(

drivers/crypto/marvell/octeontx2/otx2_cptpf.h

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ struct otx2_cptpf_dev { 
	u8 max_vfs;		/* Maximum number of VFs supported by CPT */

	u8 enabled_vfs;		/* Number of enabled VFs */

	u8 kvf_limits;		/* Kernel crypto limits */

	bool has_cpt1;

};



irqreturn_t otx2_cptpf_afpf_mbox_intr(int irq, void *arg);