Commit b074f057 authored by Stefan Agner's avatar Stefan Agner Committed by Shawn Guo
Browse files

ARM: dts: imx6qdl-apalis/-colibri: remove unused pinctrl groups 



100/200MHz states for USDHC3 are not required since the SoC
does not support modes faster than DDR52 for the on board eMMC.

Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 330f8559

arch/arm/boot/dts/imx6qdl-apalis.dtsi

+0 −34
Original line number Diff line number Diff line
@@ -947,38 +947,4 @@ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 
			MX6QDL_PAD_SD3_RST__SD3_RESET  0x17059

		>;

	};



	pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {

		fsl,pins = <

			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170b9

			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100b9

			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9

			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9

			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9

			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9

			MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9

			MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9

			MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9

			MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9

			/* eMMC reset */

			MX6QDL_PAD_SD3_RST__SD3_RESET  0x170b9

		>;

	};



	pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {

		fsl,pins = <

			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170f9

			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100f9

			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9

			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9

			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9

			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9

			MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9

			MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9

			MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9

			MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9

			/* eMMC reset */

			MX6QDL_PAD_SD3_RST__SD3_RESET  0x170f9

		>;

	};

};

arch/arm/boot/dts/imx6qdl-colibri.dtsi

+0 −34
Original line number Diff line number Diff line
@@ -692,40 +692,6 @@ MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 
		>;

	};



	pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {

		fsl,pins = <

			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x170b9

			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x100b9

			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x170b9

			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x170b9

			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x170b9

			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x170b9

			MX6QDL_PAD_SD3_DAT4__SD3_DATA4	0x170b9

			MX6QDL_PAD_SD3_DAT5__SD3_DATA5	0x170b9

			MX6QDL_PAD_SD3_DAT6__SD3_DATA6	0x170b9

			MX6QDL_PAD_SD3_DAT7__SD3_DATA7	0x170b9

			/* eMMC reset */

			MX6QDL_PAD_SD3_RST__SD3_RESET	0x170b9

		>;

	};



	pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {

		fsl,pins = <

			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x170f9

			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x100f9

			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x170f9

			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x170f9

			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x170f9

			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x170f9

			MX6QDL_PAD_SD3_DAT4__SD3_DATA4	0x170f9

			MX6QDL_PAD_SD3_DAT5__SD3_DATA5	0x170f9

			MX6QDL_PAD_SD3_DAT6__SD3_DATA6	0x170f9

			MX6QDL_PAD_SD3_DAT7__SD3_DATA7	0x170f9

			/* eMMC reset */

			MX6QDL_PAD_SD3_RST__SD3_RESET	0x170f9

		>;

	};



	pinctrl_weim_cs0: weimcs0grp {

		fsl,pins = <

			/* nEXT_CS0 */