Commit ad9469fb authored by James Zhu's avatar James Zhu Committed by Alex Deucher
Browse files

drm/amdgpu/vcn2.5: stall DPG when WPTR/RPTR reset 



Add vcn dpg harware synchronization to fix race condition
issue between vcn driver and hardware.

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ef563ff4

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

+21 −0
Original line number Diff line number Diff line
@@ -846,6 +846,12 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo 
	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

	WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_CNTL, tmp);



	/* Stall DPG before WPTR/RPTR reset */

	WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS),

		UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,

		~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);

	fw_shared->multi_queue.decode_queue_mode |= fw_queue_ring_reset;



	/* set the write pointer delay */

	WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);
@@ -868,6 +874,10 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo 
	WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR,

		lower_32_bits(ring->wptr));



	/* Unstall DPG */

	WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS),

		0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);



	return 0;

}
@@ -1380,8 +1390,14 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, 
					   UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,

					   UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);



				/* Stall DPG before WPTR/RPTR reset */

				WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS),

					   UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,

					   ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);



				/* Restore */

				ring = &adev->vcn.inst[inst_idx].ring_enc[0];

				ring->wptr = 0;

				WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);

				WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

				WREG32_SOC15(UVD, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
@@ -1389,6 +1405,7 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, 
				WREG32_SOC15(UVD, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));



				ring = &adev->vcn.inst[inst_idx].ring_enc[1];

				ring->wptr = 0;

				WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);

				WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

				WREG32_SOC15(UVD, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
@@ -1398,6 +1415,10 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, 
				WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR,

					   RREG32_SOC15(UVD, inst_idx, mmUVD_SCRATCH2) & 0x7FFFFFFF);



				/* Unstall DPG */

				WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS),

					   0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);



				SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS,

					   UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);

			}