Commit ac5ce245 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch 'kvm-arm64/host-stage2' into kvmarm-master/next 



Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents fbb31e5f b1306fef

arch/arm64/Kconfig

+0 −7
Original line number Diff line number Diff line
@@ -1684,7 +1684,6 @@ endmenu 
config ARM64_SVE

	bool "ARM Scalable Vector Extension support"

	default y

	depends on !KVM || ARM64_VHE

	help

	  The Scalable Vector Extension (SVE) is an extension to the AArch64

	  execution state which complements and extends the SIMD functionality
@@ -1713,12 +1712,6 @@ config ARM64_SVE 
	  booting the kernel.  If unsure and you are not observing these

	  symptoms, you should assume that it is safe to say Y.



	  CPUs that support SVE are architecturally required to support the

	  Virtualization Host Extensions (VHE), so the kernel makes no

	  provision for supporting SVE alongside KVM without VHE enabled.

	  Thus, you will need to enable CONFIG_ARM64_VHE if you want to support

	  KVM in the same kernel image.



config ARM64_MODULE_PLTS

	bool "Use PLTs to allow module memory to spill over into vmalloc area"

	depends on MODULES

arch/arm64/include/asm/assembler.h

+24 −3
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <asm-generic/export.h>



#include <asm/asm-offsets.h>

#include <asm/asm-bug.h>

#include <asm/cpufeature.h>

#include <asm/cputype.h>

#include <asm/debug-monitors.h>
@@ -270,12 +271,24 @@ alternative_endif 
 * provide the system wide safe value from arm64_ftr_reg_ctrel0.sys_val

 */

	.macro	read_ctr, reg

#ifndef __KVM_NVHE_HYPERVISOR__

alternative_if_not ARM64_MISMATCHED_CACHE_TYPE

	mrs	\reg, ctr_el0			// read CTR

	nop

alternative_else

	ldr_l	\reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL

alternative_endif

#else

alternative_if_not ARM64_KVM_PROTECTED_MODE

	ASM_BUG()

alternative_else_nop_endif

alternative_cb kvm_compute_final_ctr_el0

	movz	\reg, #0

	movk	\reg, #0, lsl #16

	movk	\reg, #0, lsl #32

	movk	\reg, #0, lsl #48

alternative_cb_end

#endif

	.endm
@@ -676,11 +689,11 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU 
	.endm



/*

 * Set SCTLR_EL1 to the passed value, and invalidate the local icache

 * Set SCTLR_ELx to the @reg value, and invalidate the local icache

 * in the process. This is called when setting the MMU on.

 */

.macro set_sctlr_el1, reg

	msr	sctlr_el1, \reg

.macro set_sctlr, sreg, reg

	msr	\sreg, \reg

	isb

	/*

	 * Invalidate the local I-cache so that any instructions fetched
@@ -692,6 +705,14 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU 
	isb

.endm



.macro set_sctlr_el1, reg

	set_sctlr sctlr_el1, \reg

.endm



.macro set_sctlr_el2, reg

	set_sctlr sctlr_el2, \reg

.endm



/*

 * Check whether to yield to another runnable task from kernel mode NEON code

 * (which runs with preemption disabled).

arch/arm64/include/asm/fpsimd.h

+9 −0
Original line number Diff line number Diff line
@@ -130,6 +130,15 @@ static inline void sve_user_enable(void) 
	sysreg_clear_set(cpacr_el1, 0, CPACR_EL1_ZEN_EL0EN);

}



#define sve_cond_update_zcr_vq(val, reg)		\

	do {						\

		u64 __zcr = read_sysreg_s((reg));	\

		u64 __new = __zcr & ~ZCR_ELx_LEN_MASK;	\

		__new |= (val) & ZCR_ELx_LEN_MASK;	\

		if (__zcr != __new)			\

			write_sysreg_s(__new, (reg));	\

	} while (0)



/*

 * Probing and setup functions.

 * Calls to these functions must be serialised with one another.

arch/arm64/include/asm/fpsimdmacros.h

+8 −2
Original line number Diff line number Diff line
@@ -6,6 +6,8 @@ 
 * Author: Catalin Marinas <catalin.marinas@arm.com>

 */



#include <asm/assembler.h>



.macro fpsimd_save state, tmpnr

	stp	q0, q1, [\state, #16 * 0]

	stp	q2, q3, [\state, #16 * 2]
@@ -230,8 +232,7 @@ 
		str		w\nxtmp, [\xpfpsr, #4]

.endm



.macro sve_load nxbase, xpfpsr, xvqminus1, nxtmp, xtmp2

		sve_load_vq	\xvqminus1, x\nxtmp, \xtmp2

.macro __sve_load nxbase, xpfpsr, nxtmp

 _for n, 0, 31,	_sve_ldr_v	\n, \nxbase, \n - 34

		_sve_ldr_p	0, \nxbase

		_sve_wrffr	0
@@ -242,3 +243,8 @@ 
		ldr		w\nxtmp, [\xpfpsr, #4]

		msr		fpcr, x\nxtmp

.endm



.macro sve_load nxbase, xpfpsr, xvqminus1, nxtmp, xtmp2

		sve_load_vq	\xvqminus1, x\nxtmp, \xtmp2

		__sve_load	\nxbase, \xpfpsr, \nxtmp

.endm

arch/arm64/include/asm/hyp_image.h

+7 −0
Original line number Diff line number Diff line
@@ -10,11 +10,15 @@ 
#define __HYP_CONCAT(a, b)	a ## b

#define HYP_CONCAT(a, b)	__HYP_CONCAT(a, b)



#ifndef __KVM_NVHE_HYPERVISOR__

/*

 * KVM nVHE code has its own symbol namespace prefixed with __kvm_nvhe_,

 * to separate it from the kernel proper.

 */

#define kvm_nvhe_sym(sym)	__kvm_nvhe_##sym

#else

#define kvm_nvhe_sym(sym)	sym

#endif



#ifdef LINKER_SCRIPT
@@ -56,6 +60,9 @@ 
 */

#define KVM_NVHE_ALIAS(sym)	kvm_nvhe_sym(sym) = sym;



/* Defines a linker script alias for KVM nVHE hyp symbols */

#define KVM_NVHE_ALIAS_HYP(first, sec)	kvm_nvhe_sym(first) = kvm_nvhe_sym(sec);



#endif /* LINKER_SCRIPT */



#endif /* __ARM64_HYP_IMAGE_H__ */