Commit aae10d2b authored by Chanho Park's avatar Chanho Park Committed by Krzysztof Kozlowski
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arm64: dts: exynosautov9: prepare usi0 changes 



Before adding whole USI nodes, this applies the changes of usi0 in
advance. To be the usi0 and serian_0 nodes as SoC default, some
properties should be moved to exynosautov9-sadk.dts.

Signed-off-by: default avatarChanho Park <chanho61.park@samsung.com>
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220701015226.32781-5-chanho61.park@samsung.com
parent 358ab0d1

arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts

+2 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ ufs_1_fixed_vcc_reg: regulator-1 { 
};



&serial_0 {

	pinctrl-0 = <&uart0_bus_dual>;

	status = "okay";

};
@@ -74,6 +75,7 @@ &ufs_1 { 
};



&usi_0 {

	samsung,clkreq-on; /* needed for UART mode */

	status = "okay";

};

arch/arm64/boot/dts/exynos/exynosautov9.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -352,11 +352,11 @@ syscon_peric0: syscon@10220000 { 
		};



		usi_0: usi@103000c0 {

			compatible = "samsung,exynos850-usi";

			compatible = "samsung,exynosautov9-usi",

				     "samsung,exynos850-usi";

			reg = <0x103000c0 0x20>;

			samsung,sysreg = <&syscon_peric0 0x1000>;

			samsung,mode = <USI_V2_UART>;

			samsung,clkreq-on; /* needed for UART mode */

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;
@@ -365,13 +365,13 @@ usi_0: usi@103000c0 { 
			clock-names = "pclk", "ipclk";

			status = "disabled";



			/* USI: UART */

			serial_0: serial@10300000 {

				compatible = "samsung,exynos850-uart";

				compatible = "samsung,exynosautov9-uart",

					     "samsung,exynos850-uart";

				reg = <0x10300000 0xc0>;

				interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;

				pinctrl-names = "default";

				pinctrl-0 = <&uart0_bus_dual>;

				pinctrl-0 = <&uart0_bus>;

				clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>,

					 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>;

				clock-names = "uart", "clk_uart_baud0";