Commit aa32a955 authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: Octeon: Update register definitions for CN63XX chips 



The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores.

Join some lines back together.  This makes some of them exceed 80
columns, but they are uninteresting and this unclutters things.

Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1668/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent b93b2abc

arch/mips/include/asm/octeon/cvmx-agl-defs.h

+434 −182

File changed.

Preview size limit exceeded, changes collapsed.

arch/mips/include/asm/octeon/cvmx-ciu-defs.h

+769 −88

File changed.

Preview size limit exceeded, changes collapsed.

arch/mips/include/asm/octeon/cvmx-gpio-defs.h

+50 −24
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 
 * Contact: support@caviumnetworks.com

 * This file is part of the OCTEON SDK

 *

 * Copyright (c) 2003-2008 Cavium Networks

 * Copyright (c) 2003-2010 Cavium Networks

 *

 * This file is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,29 +28,22 @@ 
#ifndef __CVMX_GPIO_DEFS_H__

#define __CVMX_GPIO_DEFS_H__



#define CVMX_GPIO_BIT_CFGX(offset) \

	 CVMX_ADD_IO_SEG(0x0001070000000800ull + (((offset) & 15) * 8))

#define CVMX_GPIO_BOOT_ENA \

	 CVMX_ADD_IO_SEG(0x00010700000008A8ull)

#define CVMX_GPIO_CLK_GENX(offset) \

	 CVMX_ADD_IO_SEG(0x00010700000008C0ull + (((offset) & 3) * 8))

#define CVMX_GPIO_DBG_ENA \

	 CVMX_ADD_IO_SEG(0x00010700000008A0ull)

#define CVMX_GPIO_INT_CLR \

	 CVMX_ADD_IO_SEG(0x0001070000000898ull)

#define CVMX_GPIO_RX_DAT \

	 CVMX_ADD_IO_SEG(0x0001070000000880ull)

#define CVMX_GPIO_TX_CLR \

	 CVMX_ADD_IO_SEG(0x0001070000000890ull)

#define CVMX_GPIO_TX_SET \

	 CVMX_ADD_IO_SEG(0x0001070000000888ull)

#define CVMX_GPIO_XBIT_CFGX(offset) \

	 CVMX_ADD_IO_SEG(0x0001070000000900ull + (((offset) & 31) * 8) - 8 * 16)

#define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)

#define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))

#define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)

#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)

#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))

#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))

#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))

#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))

#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))

#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)



union cvmx_gpio_bit_cfgx {

	uint64_t u64;

	struct cvmx_gpio_bit_cfgx_s {

		uint64_t reserved_15_63:49;

		uint64_t reserved_17_63:47;

		uint64_t synce_sel:2;

		uint64_t clk_gen:1;

		uint64_t clk_sel:2;

		uint64_t fil_sel:4;
@@ -73,12 +66,24 @@ union cvmx_gpio_bit_cfgx { 
	struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;

	struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;

	struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;

	struct cvmx_gpio_bit_cfgx_s cn52xx;

	struct cvmx_gpio_bit_cfgx_s cn52xxp1;

	struct cvmx_gpio_bit_cfgx_s cn56xx;

	struct cvmx_gpio_bit_cfgx_s cn56xxp1;

	struct cvmx_gpio_bit_cfgx_cn52xx {

		uint64_t reserved_15_63:49;

		uint64_t clk_gen:1;

		uint64_t clk_sel:2;

		uint64_t fil_sel:4;

		uint64_t fil_cnt:4;

		uint64_t int_type:1;

		uint64_t int_en:1;

		uint64_t rx_xor:1;

		uint64_t tx_oe:1;

	} cn52xx;

	struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1;

	struct cvmx_gpio_bit_cfgx_cn52xx cn56xx;

	struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1;

	struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;

	struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;

	struct cvmx_gpio_bit_cfgx_s cn63xx;

	struct cvmx_gpio_bit_cfgx_s cn63xxp1;

};



union cvmx_gpio_boot_ena {
@@ -103,6 +108,19 @@ union cvmx_gpio_clk_genx { 
	struct cvmx_gpio_clk_genx_s cn52xxp1;

	struct cvmx_gpio_clk_genx_s cn56xx;

	struct cvmx_gpio_clk_genx_s cn56xxp1;

	struct cvmx_gpio_clk_genx_s cn63xx;

	struct cvmx_gpio_clk_genx_s cn63xxp1;

};



union cvmx_gpio_clk_qlmx {

	uint64_t u64;

	struct cvmx_gpio_clk_qlmx_s {

		uint64_t reserved_3_63:61;

		uint64_t div:1;

		uint64_t lane_sel:2;

	} s;

	struct cvmx_gpio_clk_qlmx_s cn63xx;

	struct cvmx_gpio_clk_qlmx_s cn63xxp1;

};



union cvmx_gpio_dbg_ena {
@@ -133,6 +151,8 @@ union cvmx_gpio_int_clr { 
	struct cvmx_gpio_int_clr_s cn56xxp1;

	struct cvmx_gpio_int_clr_s cn58xx;

	struct cvmx_gpio_int_clr_s cn58xxp1;

	struct cvmx_gpio_int_clr_s cn63xx;

	struct cvmx_gpio_int_clr_s cn63xxp1;

};



union cvmx_gpio_rx_dat {
@@ -155,6 +175,8 @@ union cvmx_gpio_rx_dat { 
	struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;

	struct cvmx_gpio_rx_dat_cn38xx cn58xx;

	struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;

	struct cvmx_gpio_rx_dat_cn38xx cn63xx;

	struct cvmx_gpio_rx_dat_cn38xx cn63xxp1;

};



union cvmx_gpio_tx_clr {
@@ -177,6 +199,8 @@ union cvmx_gpio_tx_clr { 
	struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;

	struct cvmx_gpio_tx_clr_cn38xx cn58xx;

	struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;

	struct cvmx_gpio_tx_clr_cn38xx cn63xx;

	struct cvmx_gpio_tx_clr_cn38xx cn63xxp1;

};



union cvmx_gpio_tx_set {
@@ -199,6 +223,8 @@ union cvmx_gpio_tx_set { 
	struct cvmx_gpio_tx_set_cn38xx cn56xxp1;

	struct cvmx_gpio_tx_set_cn38xx cn58xx;

	struct cvmx_gpio_tx_set_cn38xx cn58xxp1;

	struct cvmx_gpio_tx_set_cn38xx cn63xx;

	struct cvmx_gpio_tx_set_cn38xx cn63xxp1;

};



union cvmx_gpio_xbit_cfgx {

arch/mips/include/asm/octeon/cvmx-iob-defs.h

+162 −80
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 
 * Contact: support@caviumnetworks.com

 * This file is part of the OCTEON SDK

 *

 * Copyright (c) 2003-2008 Cavium Networks

 * Copyright (c) 2003-2010 Cavium Networks

 *

 * This file is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,55 +28,39 @@ 
#ifndef __CVMX_IOB_DEFS_H__

#define __CVMX_IOB_DEFS_H__



#define CVMX_IOB_BIST_STATUS \

	 CVMX_ADD_IO_SEG(0x00011800F00007F8ull)

#define CVMX_IOB_CTL_STATUS \

	 CVMX_ADD_IO_SEG(0x00011800F0000050ull)

#define CVMX_IOB_DWB_PRI_CNT \

	 CVMX_ADD_IO_SEG(0x00011800F0000028ull)

#define CVMX_IOB_FAU_TIMEOUT \

	 CVMX_ADD_IO_SEG(0x00011800F0000000ull)

#define CVMX_IOB_I2C_PRI_CNT \

	 CVMX_ADD_IO_SEG(0x00011800F0000010ull)

#define CVMX_IOB_INB_CONTROL_MATCH \

	 CVMX_ADD_IO_SEG(0x00011800F0000078ull)

#define CVMX_IOB_INB_CONTROL_MATCH_ENB \

	 CVMX_ADD_IO_SEG(0x00011800F0000088ull)

#define CVMX_IOB_INB_DATA_MATCH \

	 CVMX_ADD_IO_SEG(0x00011800F0000070ull)

#define CVMX_IOB_INB_DATA_MATCH_ENB \

	 CVMX_ADD_IO_SEG(0x00011800F0000080ull)

#define CVMX_IOB_INT_ENB \

	 CVMX_ADD_IO_SEG(0x00011800F0000060ull)

#define CVMX_IOB_INT_SUM \

	 CVMX_ADD_IO_SEG(0x00011800F0000058ull)

#define CVMX_IOB_N2C_L2C_PRI_CNT \

	 CVMX_ADD_IO_SEG(0x00011800F0000020ull)

#define CVMX_IOB_N2C_RSP_PRI_CNT \

	 CVMX_ADD_IO_SEG(0x00011800F0000008ull)

#define CVMX_IOB_OUTB_COM_PRI_CNT \

	 CVMX_ADD_IO_SEG(0x00011800F0000040ull)

#define CVMX_IOB_OUTB_CONTROL_MATCH \

	 CVMX_ADD_IO_SEG(0x00011800F0000098ull)

#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB \

	 CVMX_ADD_IO_SEG(0x00011800F00000A8ull)

#define CVMX_IOB_OUTB_DATA_MATCH \

	 CVMX_ADD_IO_SEG(0x00011800F0000090ull)

#define CVMX_IOB_OUTB_DATA_MATCH_ENB \

	 CVMX_ADD_IO_SEG(0x00011800F00000A0ull)

#define CVMX_IOB_OUTB_FPA_PRI_CNT \

	 CVMX_ADD_IO_SEG(0x00011800F0000048ull)

#define CVMX_IOB_OUTB_REQ_PRI_CNT \

	 CVMX_ADD_IO_SEG(0x00011800F0000038ull)

#define CVMX_IOB_P2C_REQ_PRI_CNT \

	 CVMX_ADD_IO_SEG(0x00011800F0000018ull)

#define CVMX_IOB_PKT_ERR \

	 CVMX_ADD_IO_SEG(0x00011800F0000068ull)

#define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull))

#define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull))

#define CVMX_IOB_DWB_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000028ull))

#define CVMX_IOB_FAU_TIMEOUT (CVMX_ADD_IO_SEG(0x00011800F0000000ull))

#define CVMX_IOB_I2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000010ull))

#define CVMX_IOB_INB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000078ull))

#define CVMX_IOB_INB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000088ull))

#define CVMX_IOB_INB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000070ull))

#define CVMX_IOB_INB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000080ull))

#define CVMX_IOB_INT_ENB (CVMX_ADD_IO_SEG(0x00011800F0000060ull))

#define CVMX_IOB_INT_SUM (CVMX_ADD_IO_SEG(0x00011800F0000058ull))

#define CVMX_IOB_N2C_L2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000020ull))

#define CVMX_IOB_N2C_RSP_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000008ull))

#define CVMX_IOB_OUTB_COM_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000040ull))

#define CVMX_IOB_OUTB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000098ull))

#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A8ull))

#define CVMX_IOB_OUTB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000090ull))

#define CVMX_IOB_OUTB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A0ull))

#define CVMX_IOB_OUTB_FPA_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000048ull))

#define CVMX_IOB_OUTB_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000038ull))

#define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull))

#define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull))

#define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull))



union cvmx_iob_bist_status {

	uint64_t u64;

	struct cvmx_iob_bist_status_s {

		uint64_t reserved_18_63:46;

		uint64_t reserved_23_63:41;

		uint64_t xmdfif:1;

		uint64_t xmcfif:1;

		uint64_t iorfif:1;

		uint64_t rsdfif:1;

		uint64_t iocfif:1;

		uint64_t icnrcb:1;

		uint64_t icr0:1;

		uint64_t icr1:1;
@@ -96,40 +80,81 @@ union cvmx_iob_bist_status { 
		uint64_t ibd:1;

		uint64_t icd:1;

	} s;

	struct cvmx_iob_bist_status_s cn30xx;

	struct cvmx_iob_bist_status_s cn31xx;

	struct cvmx_iob_bist_status_s cn38xx;

	struct cvmx_iob_bist_status_s cn38xxp2;

	struct cvmx_iob_bist_status_s cn50xx;

	struct cvmx_iob_bist_status_s cn52xx;

	struct cvmx_iob_bist_status_s cn52xxp1;

	struct cvmx_iob_bist_status_s cn56xx;

	struct cvmx_iob_bist_status_s cn56xxp1;

	struct cvmx_iob_bist_status_s cn58xx;

	struct cvmx_iob_bist_status_s cn58xxp1;

	struct cvmx_iob_bist_status_cn30xx {

		uint64_t reserved_18_63:46;

		uint64_t icnrcb:1;

		uint64_t icr0:1;

		uint64_t icr1:1;

		uint64_t icnr1:1;

		uint64_t icnr0:1;

		uint64_t ibdr0:1;

		uint64_t ibdr1:1;

		uint64_t ibr0:1;

		uint64_t ibr1:1;

		uint64_t icnrt:1;

		uint64_t ibrq0:1;

		uint64_t ibrq1:1;

		uint64_t icrn0:1;

		uint64_t icrn1:1;

		uint64_t icrp0:1;

		uint64_t icrp1:1;

		uint64_t ibd:1;

		uint64_t icd:1;

	} cn30xx;

	struct cvmx_iob_bist_status_cn30xx cn31xx;

	struct cvmx_iob_bist_status_cn30xx cn38xx;

	struct cvmx_iob_bist_status_cn30xx cn38xxp2;

	struct cvmx_iob_bist_status_cn30xx cn50xx;

	struct cvmx_iob_bist_status_cn30xx cn52xx;

	struct cvmx_iob_bist_status_cn30xx cn52xxp1;

	struct cvmx_iob_bist_status_cn30xx cn56xx;

	struct cvmx_iob_bist_status_cn30xx cn56xxp1;

	struct cvmx_iob_bist_status_cn30xx cn58xx;

	struct cvmx_iob_bist_status_cn30xx cn58xxp1;

	struct cvmx_iob_bist_status_s cn63xx;

	struct cvmx_iob_bist_status_s cn63xxp1;

};



union cvmx_iob_ctl_status {

	uint64_t u64;

	struct cvmx_iob_ctl_status_s {

		uint64_t reserved_5_63:59;

		uint64_t reserved_10_63:54;

		uint64_t xmc_per:4;

		uint64_t rr_mode:1;

		uint64_t outb_mat:1;

		uint64_t inb_mat:1;

		uint64_t pko_enb:1;

		uint64_t dwb_enb:1;

		uint64_t fau_end:1;

	} s;

	struct cvmx_iob_ctl_status_s cn30xx;

	struct cvmx_iob_ctl_status_s cn31xx;

	struct cvmx_iob_ctl_status_s cn38xx;

	struct cvmx_iob_ctl_status_s cn38xxp2;

	struct cvmx_iob_ctl_status_s cn50xx;

	struct cvmx_iob_ctl_status_s cn52xx;

	struct cvmx_iob_ctl_status_s cn52xxp1;

	struct cvmx_iob_ctl_status_s cn56xx;

	struct cvmx_iob_ctl_status_s cn56xxp1;

	struct cvmx_iob_ctl_status_s cn58xx;

	struct cvmx_iob_ctl_status_s cn58xxp1;

	struct cvmx_iob_ctl_status_cn30xx {

		uint64_t reserved_5_63:59;

		uint64_t outb_mat:1;

		uint64_t inb_mat:1;

		uint64_t pko_enb:1;

		uint64_t dwb_enb:1;

		uint64_t fau_end:1;

	} cn30xx;

	struct cvmx_iob_ctl_status_cn30xx cn31xx;

	struct cvmx_iob_ctl_status_cn30xx cn38xx;

	struct cvmx_iob_ctl_status_cn30xx cn38xxp2;

	struct cvmx_iob_ctl_status_cn30xx cn50xx;

	struct cvmx_iob_ctl_status_cn52xx {

		uint64_t reserved_6_63:58;

		uint64_t rr_mode:1;

		uint64_t outb_mat:1;

		uint64_t inb_mat:1;

		uint64_t pko_enb:1;

		uint64_t dwb_enb:1;

		uint64_t fau_end:1;

	} cn52xx;

	struct cvmx_iob_ctl_status_cn30xx cn52xxp1;

	struct cvmx_iob_ctl_status_cn30xx cn56xx;

	struct cvmx_iob_ctl_status_cn30xx cn56xxp1;

	struct cvmx_iob_ctl_status_cn30xx cn58xx;

	struct cvmx_iob_ctl_status_cn30xx cn58xxp1;

	struct cvmx_iob_ctl_status_s cn63xx;

	struct cvmx_iob_ctl_status_s cn63xxp1;

};



union cvmx_iob_dwb_pri_cnt {
@@ -147,6 +172,8 @@ union cvmx_iob_dwb_pri_cnt { 
	struct cvmx_iob_dwb_pri_cnt_s cn56xxp1;

	struct cvmx_iob_dwb_pri_cnt_s cn58xx;

	struct cvmx_iob_dwb_pri_cnt_s cn58xxp1;

	struct cvmx_iob_dwb_pri_cnt_s cn63xx;

	struct cvmx_iob_dwb_pri_cnt_s cn63xxp1;

};



union cvmx_iob_fau_timeout {
@@ -167,6 +194,8 @@ union cvmx_iob_fau_timeout { 
	struct cvmx_iob_fau_timeout_s cn56xxp1;

	struct cvmx_iob_fau_timeout_s cn58xx;

	struct cvmx_iob_fau_timeout_s cn58xxp1;

	struct cvmx_iob_fau_timeout_s cn63xx;

	struct cvmx_iob_fau_timeout_s cn63xxp1;

};



union cvmx_iob_i2c_pri_cnt {
@@ -184,6 +213,8 @@ union cvmx_iob_i2c_pri_cnt { 
	struct cvmx_iob_i2c_pri_cnt_s cn56xxp1;

	struct cvmx_iob_i2c_pri_cnt_s cn58xx;

	struct cvmx_iob_i2c_pri_cnt_s cn58xxp1;

	struct cvmx_iob_i2c_pri_cnt_s cn63xx;

	struct cvmx_iob_i2c_pri_cnt_s cn63xxp1;

};



union cvmx_iob_inb_control_match {
@@ -206,6 +237,8 @@ union cvmx_iob_inb_control_match { 
	struct cvmx_iob_inb_control_match_s cn56xxp1;

	struct cvmx_iob_inb_control_match_s cn58xx;

	struct cvmx_iob_inb_control_match_s cn58xxp1;

	struct cvmx_iob_inb_control_match_s cn63xx;

	struct cvmx_iob_inb_control_match_s cn63xxp1;

};



union cvmx_iob_inb_control_match_enb {
@@ -228,6 +261,8 @@ union cvmx_iob_inb_control_match_enb { 
	struct cvmx_iob_inb_control_match_enb_s cn56xxp1;

	struct cvmx_iob_inb_control_match_enb_s cn58xx;

	struct cvmx_iob_inb_control_match_enb_s cn58xxp1;

	struct cvmx_iob_inb_control_match_enb_s cn63xx;

	struct cvmx_iob_inb_control_match_enb_s cn63xxp1;

};



union cvmx_iob_inb_data_match {
@@ -246,6 +281,8 @@ union cvmx_iob_inb_data_match { 
	struct cvmx_iob_inb_data_match_s cn56xxp1;

	struct cvmx_iob_inb_data_match_s cn58xx;

	struct cvmx_iob_inb_data_match_s cn58xxp1;

	struct cvmx_iob_inb_data_match_s cn63xx;

	struct cvmx_iob_inb_data_match_s cn63xxp1;

};



union cvmx_iob_inb_data_match_enb {
@@ -264,6 +301,8 @@ union cvmx_iob_inb_data_match_enb { 
	struct cvmx_iob_inb_data_match_enb_s cn56xxp1;

	struct cvmx_iob_inb_data_match_enb_s cn58xx;

	struct cvmx_iob_inb_data_match_enb_s cn58xxp1;

	struct cvmx_iob_inb_data_match_enb_s cn63xx;

	struct cvmx_iob_inb_data_match_enb_s cn63xxp1;

};



union cvmx_iob_int_enb {
@@ -294,6 +333,8 @@ union cvmx_iob_int_enb { 
	struct cvmx_iob_int_enb_s cn56xxp1;

	struct cvmx_iob_int_enb_s cn58xx;

	struct cvmx_iob_int_enb_s cn58xxp1;

	struct cvmx_iob_int_enb_s cn63xx;

	struct cvmx_iob_int_enb_s cn63xxp1;

};



union cvmx_iob_int_sum {
@@ -324,6 +365,8 @@ union cvmx_iob_int_sum { 
	struct cvmx_iob_int_sum_s cn56xxp1;

	struct cvmx_iob_int_sum_s cn58xx;

	struct cvmx_iob_int_sum_s cn58xxp1;

	struct cvmx_iob_int_sum_s cn63xx;

	struct cvmx_iob_int_sum_s cn63xxp1;

};



union cvmx_iob_n2c_l2c_pri_cnt {
@@ -341,6 +384,8 @@ union cvmx_iob_n2c_l2c_pri_cnt { 
	struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1;

	struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx;

	struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1;

	struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xx;

	struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xxp1;

};



union cvmx_iob_n2c_rsp_pri_cnt {
@@ -358,6 +403,8 @@ union cvmx_iob_n2c_rsp_pri_cnt { 
	struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1;

	struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx;

	struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1;

	struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xx;

	struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xxp1;

};



union cvmx_iob_outb_com_pri_cnt {
@@ -375,6 +422,8 @@ union cvmx_iob_outb_com_pri_cnt { 
	struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1;

	struct cvmx_iob_outb_com_pri_cnt_s cn58xx;

	struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1;

	struct cvmx_iob_outb_com_pri_cnt_s cn63xx;

	struct cvmx_iob_outb_com_pri_cnt_s cn63xxp1;

};



union cvmx_iob_outb_control_match {
@@ -397,6 +446,8 @@ union cvmx_iob_outb_control_match { 
	struct cvmx_iob_outb_control_match_s cn56xxp1;

	struct cvmx_iob_outb_control_match_s cn58xx;

	struct cvmx_iob_outb_control_match_s cn58xxp1;

	struct cvmx_iob_outb_control_match_s cn63xx;

	struct cvmx_iob_outb_control_match_s cn63xxp1;

};



union cvmx_iob_outb_control_match_enb {
@@ -419,6 +470,8 @@ union cvmx_iob_outb_control_match_enb { 
	struct cvmx_iob_outb_control_match_enb_s cn56xxp1;

	struct cvmx_iob_outb_control_match_enb_s cn58xx;

	struct cvmx_iob_outb_control_match_enb_s cn58xxp1;

	struct cvmx_iob_outb_control_match_enb_s cn63xx;

	struct cvmx_iob_outb_control_match_enb_s cn63xxp1;

};



union cvmx_iob_outb_data_match {
@@ -437,6 +490,8 @@ union cvmx_iob_outb_data_match { 
	struct cvmx_iob_outb_data_match_s cn56xxp1;

	struct cvmx_iob_outb_data_match_s cn58xx;

	struct cvmx_iob_outb_data_match_s cn58xxp1;

	struct cvmx_iob_outb_data_match_s cn63xx;

	struct cvmx_iob_outb_data_match_s cn63xxp1;

};



union cvmx_iob_outb_data_match_enb {
@@ -455,6 +510,8 @@ union cvmx_iob_outb_data_match_enb { 
	struct cvmx_iob_outb_data_match_enb_s cn56xxp1;

	struct cvmx_iob_outb_data_match_enb_s cn58xx;

	struct cvmx_iob_outb_data_match_enb_s cn58xxp1;

	struct cvmx_iob_outb_data_match_enb_s cn63xx;

	struct cvmx_iob_outb_data_match_enb_s cn63xxp1;

};



union cvmx_iob_outb_fpa_pri_cnt {
@@ -472,6 +529,8 @@ union cvmx_iob_outb_fpa_pri_cnt { 
	struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1;

	struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx;

	struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1;

	struct cvmx_iob_outb_fpa_pri_cnt_s cn63xx;

	struct cvmx_iob_outb_fpa_pri_cnt_s cn63xxp1;

};



union cvmx_iob_outb_req_pri_cnt {
@@ -489,6 +548,8 @@ union cvmx_iob_outb_req_pri_cnt { 
	struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1;

	struct cvmx_iob_outb_req_pri_cnt_s cn58xx;

	struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1;

	struct cvmx_iob_outb_req_pri_cnt_s cn63xx;

	struct cvmx_iob_outb_req_pri_cnt_s cn63xxp1;

};



union cvmx_iob_p2c_req_pri_cnt {
@@ -506,25 +567,46 @@ union cvmx_iob_p2c_req_pri_cnt { 
	struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1;

	struct cvmx_iob_p2c_req_pri_cnt_s cn58xx;

	struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1;

	struct cvmx_iob_p2c_req_pri_cnt_s cn63xx;

	struct cvmx_iob_p2c_req_pri_cnt_s cn63xxp1;

};



union cvmx_iob_pkt_err {

	uint64_t u64;

	struct cvmx_iob_pkt_err_s {

		uint64_t reserved_12_63:52;

		uint64_t vport:6;

		uint64_t port:6;

	} s;

	struct cvmx_iob_pkt_err_cn30xx {

		uint64_t reserved_6_63:58;

		uint64_t port:6;

	} cn30xx;

	struct cvmx_iob_pkt_err_cn30xx cn31xx;

	struct cvmx_iob_pkt_err_cn30xx cn38xx;

	struct cvmx_iob_pkt_err_cn30xx cn38xxp2;

	struct cvmx_iob_pkt_err_cn30xx cn50xx;

	struct cvmx_iob_pkt_err_cn30xx cn52xx;

	struct cvmx_iob_pkt_err_cn30xx cn52xxp1;

	struct cvmx_iob_pkt_err_cn30xx cn56xx;

	struct cvmx_iob_pkt_err_cn30xx cn56xxp1;

	struct cvmx_iob_pkt_err_cn30xx cn58xx;

	struct cvmx_iob_pkt_err_cn30xx cn58xxp1;

	struct cvmx_iob_pkt_err_s cn63xx;

	struct cvmx_iob_pkt_err_s cn63xxp1;

};



union cvmx_iob_to_cmb_credits {

	uint64_t u64;

	struct cvmx_iob_to_cmb_credits_s {

		uint64_t reserved_9_63:55;

		uint64_t pko_rd:3;

		uint64_t ncb_rd:3;

		uint64_t ncb_wr:3;

	} s;

	struct cvmx_iob_pkt_err_s cn30xx;

	struct cvmx_iob_pkt_err_s cn31xx;

	struct cvmx_iob_pkt_err_s cn38xx;

	struct cvmx_iob_pkt_err_s cn38xxp2;

	struct cvmx_iob_pkt_err_s cn50xx;

	struct cvmx_iob_pkt_err_s cn52xx;

	struct cvmx_iob_pkt_err_s cn52xxp1;

	struct cvmx_iob_pkt_err_s cn56xx;

	struct cvmx_iob_pkt_err_s cn56xxp1;

	struct cvmx_iob_pkt_err_s cn58xx;

	struct cvmx_iob_pkt_err_s cn58xxp1;

	struct cvmx_iob_to_cmb_credits_s cn52xx;

	struct cvmx_iob_to_cmb_credits_s cn63xx;

	struct cvmx_iob_to_cmb_credits_s cn63xxp1;

};



#endif

arch/mips/include/asm/octeon/cvmx-ipd-defs.h

+198 −116

File changed.

Preview size limit exceeded, changes collapsed.