Commit aa0813b1 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/pps: move pps (panel) modeset asserts to intel_pps.c 



Move assert_panel_unlocked() to intel_pps.c and rename
assert_pps_unlocked(). Keep the functionality and the assert code
together.

There's still a bit of a split between the eDP PPS usage in intel_pps.c
and all the other PPS usage, and assert_pps_unlocked() is arguably more
related to the latter. However, intel_pps.c is the best fit for anything
touching the PPS registers.

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/a9b77692a145891789eefb0447e082cfc22aaa85.1632992608.git.jani.nikula@intel.com
parent e04a911f

drivers/gpu/drm/i915/display/intel_display.c

+1 −59
Original line number Diff line number Diff line
@@ -428,64 +428,6 @@ void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) 
			onoff(state), onoff(cur_state));

}



void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)

{

	i915_reg_t pp_reg;

	u32 val;

	enum pipe panel_pipe = INVALID_PIPE;

	bool locked = true;



	if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))

		return;



	if (HAS_PCH_SPLIT(dev_priv)) {

		u32 port_sel;



		pp_reg = PP_CONTROL(0);

		port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;



		switch (port_sel) {

		case PANEL_PORT_SELECT_LVDS:

			intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);

			break;

		case PANEL_PORT_SELECT_DPA:

			g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);

			break;

		case PANEL_PORT_SELECT_DPC:

			g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);

			break;

		case PANEL_PORT_SELECT_DPD:

			g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);

			break;

		default:

			MISSING_CASE(port_sel);

			break;

		}

	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		/* presumably write lock depends on pipe, not port select */

		pp_reg = PP_CONTROL(pipe);

		panel_pipe = pipe;

	} else {

		u32 port_sel;



		pp_reg = PP_CONTROL(0);

		port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;



		drm_WARN_ON(&dev_priv->drm,

			    port_sel != PANEL_PORT_SELECT_LVDS);

		intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);

	}



	val = intel_de_read(dev_priv, pp_reg);

	if (!(val & PANEL_POWER_ON) ||

	    ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))

		locked = false;



	I915_STATE_WARN(panel_pipe == pipe && locked,

	     "panel assertion failure, pipe %c regs locked\n",

	     pipe_name(pipe));

}



void assert_transcoder(struct drm_i915_private *dev_priv,

		       enum transcoder cpu_transcoder, bool state)

{
@@ -2128,7 +2070,7 @@ static void ilk_pch_enable(const struct intel_atomic_state *state, 
	intel_enable_shared_dpll(crtc_state);



	/* set transcoder timing, panel must allow it */

	assert_panel_unlocked(dev_priv, pipe);

	assert_pps_unlocked(dev_priv, pipe);

	ilk_pch_transcoder_set_timings(crtc_state, pipe);



	intel_fdi_normal_train(crtc);

drivers/gpu/drm/i915/display/intel_display.h

+0 −2
Original line number Diff line number Diff line
@@ -645,8 +645,6 @@ void intel_init_pch_refclk(struct drm_i915_private *dev_priv); 
int intel_modeset_all_pipes(struct intel_atomic_state *state);



/* modesetting asserts */

void assert_panel_unlocked(struct drm_i915_private *dev_priv,

			   enum pipe pipe);

void assert_pll(struct drm_i915_private *dev_priv,

		enum pipe pipe, bool state);

#define assert_pll_enabled(d, p) assert_pll(d, p, true)

drivers/gpu/drm/i915/display/intel_dpll.c

+8 −5
Original line number Diff line number Diff line
@@ -2,16 +2,19 @@ 
/*

 * Copyright © 2020 Intel Corporation

 */



#include <linux/kernel.h>



#include "intel_crtc.h"

#include "intel_de.h"

#include "intel_display_types.h"

#include "intel_display.h"

#include "intel_display_types.h"

#include "intel_dpll.h"

#include "intel_lvds.h"

#include "intel_panel.h"

#include "intel_pps.h"

#include "intel_sideband.h"

#include "display/intel_snps_phy.h"

#include "intel_snps_phy.h"



struct intel_limit {

	struct {
@@ -1438,7 +1441,7 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) 


	/* PLL is protected by panel, make sure we can write it */

	if (i9xx_has_pps(dev_priv))

		assert_panel_unlocked(dev_priv, pipe);

		assert_pps_unlocked(dev_priv, pipe);



	intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0);

	intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1);
@@ -1617,7 +1620,7 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state) 
	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);



	/* PLL is protected by panel, make sure we can write it */

	assert_panel_unlocked(dev_priv, pipe);

	assert_pps_unlocked(dev_priv, pipe);



	/* Enable Refclk */

	intel_de_write(dev_priv, DPLL(pipe),
@@ -1769,7 +1772,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) 
	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);



	/* PLL is protected by panel, make sure we can write it */

	assert_panel_unlocked(dev_priv, pipe);

	assert_pps_unlocked(dev_priv, pipe);



	/* Enable Refclk and SSC */

	intel_de_write(dev_priv, DPLL(pipe),

drivers/gpu/drm/i915/display/intel_pps.c

+59 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include "intel_display_types.h"

#include "intel_dp.h"

#include "intel_dpll.h"

#include "intel_lvds.h"

#include "intel_pps.h"



static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
@@ -1408,3 +1409,61 @@ void intel_pps_setup(struct drm_i915_private *i915) 
	else

		i915->pps_mmio_base = PPS_BASE;

}



void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)

{

	i915_reg_t pp_reg;

	u32 val;

	enum pipe panel_pipe = INVALID_PIPE;

	bool locked = true;



	if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))

		return;



	if (HAS_PCH_SPLIT(dev_priv)) {

		u32 port_sel;



		pp_reg = PP_CONTROL(0);

		port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;



		switch (port_sel) {

		case PANEL_PORT_SELECT_LVDS:

			intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);

			break;

		case PANEL_PORT_SELECT_DPA:

			g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);

			break;

		case PANEL_PORT_SELECT_DPC:

			g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);

			break;

		case PANEL_PORT_SELECT_DPD:

			g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);

			break;

		default:

			MISSING_CASE(port_sel);

			break;

		}

	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		/* presumably write lock depends on pipe, not port select */

		pp_reg = PP_CONTROL(pipe);

		panel_pipe = pipe;

	} else {

		u32 port_sel;



		pp_reg = PP_CONTROL(0);

		port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;



		drm_WARN_ON(&dev_priv->drm,

			    port_sel != PANEL_PORT_SELECT_LVDS);

		intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);

	}



	val = intel_de_read(dev_priv, pp_reg);

	if (!(val & PANEL_POWER_ON) ||

	    ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))

		locked = false;



	I915_STATE_WARN(panel_pipe == pipe && locked,

			"panel assertion failure, pipe %c regs locked\n",

			pipe_name(pipe));

}

drivers/gpu/drm/i915/display/intel_pps.h

+3 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 


#include "intel_wakeref.h"



enum pipe;

struct drm_i915_private;

struct intel_connector;

struct intel_crtc_state;
@@ -49,4 +50,6 @@ void vlv_pps_init(struct intel_encoder *encoder, 
void intel_pps_unlock_regs_wa(struct drm_i915_private *i915);

void intel_pps_setup(struct drm_i915_private *i915);



void assert_pps_unlocked(struct drm_i915_private *i915, enum pipe pipe);



#endif /* __INTEL_PPS_H__ */