Unverified Commit a9429d5f authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "RISC-V: Enable cbo.zero in usermode" 

Andrew Jones <ajones@ventanamicro.com> says:

In order for usermode to issue cbo.zero, it needs privilege granted to
issue the extension instruction (patch 2) and to know that the extension
is available and its block size (patch 3). Patch 1 could be separate from
this series (it just fixes up some error messages), patches 4-5 convert
the hwprobe selftest to a statically-linked, TAP test and patch 6 adds a
new hwprobe test for the new information as well as testing CBO
instructions can or cannot be issued as appropriate.

* b4-shazam-merge:
  RISC-V: selftests: Add CBO tests
  RISC-V: selftests: Convert hwprobe test to kselftest API
  RISC-V: selftests: Statically link hwprobe test
  RISC-V: hwprobe: Expose Zicboz extension and its block size
  RISC-V: Enable cbo.zero in usermode
  RISC-V: Make zicbom/zicboz errors consistent

Link: https://lore.kernel.org/r/20230918131518.56803-8-ajones@ventanamicro.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents 71e11d06 a29e2a48

Documentation/riscv/hwprobe.rst

+6 −0
Original line number Diff line number Diff line
@@ -77,6 +77,9 @@ The following keys are defined: 
  * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined

       in version 1.0 of the Bit-Manipulation ISA extensions.



  * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as

       ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.
@@ -96,3 +99,6 @@ The following keys are defined: 


  * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are

    not supported at all and will generate a misaligned address fault.



* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which

  represents the size of the Zicboz block in bytes.

arch/riscv/include/asm/cpufeature.h

+1 −0
Original line number Diff line number Diff line
@@ -31,5 +31,6 @@ DECLARE_PER_CPU(long, misaligned_access_speed); 
extern struct riscv_isainfo hart_isa[NR_CPUS];



void check_unaligned_access(int cpu);

void riscv_user_isa_enable(void);



#endif

arch/riscv/include/asm/csr.h

+1 −0
Original line number Diff line number Diff line
@@ -275,6 +275,7 @@ 
#define CSR_SIE			0x104

#define CSR_STVEC		0x105

#define CSR_SCOUNTEREN		0x106

#define CSR_SENVCFG		0x10a

#define CSR_SSCRATCH		0x140

#define CSR_SEPC		0x141

#define CSR_SCAUSE		0x142

arch/riscv/include/asm/hwcap.h

+16 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ 
#ifndef __ASSEMBLY__



#include <linux/jump_label.h>

#include <asm/cpufeature.h>



unsigned long riscv_get_elf_hwcap(void);
@@ -137,6 +138,21 @@ riscv_has_extension_unlikely(const unsigned long ext) 
	return true;

}



static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)

{

	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext))

		return true;



	return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);

}



static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext)

{

	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext))

		return true;



	return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);

}

#endif



#endif /* _ASM_RISCV_HWCAP_H */

arch/riscv/include/asm/hwprobe.h

+1 −1
Original line number Diff line number Diff line
@@ -8,6 +8,6 @@ 


#include <uapi/asm/hwprobe.h>



#define RISCV_HWPROBE_MAX_KEY 5

#define RISCV_HWPROBE_MAX_KEY 6



#endif