Commit a7f520bf authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: derive GTT display support from DM 



Rather than duplicating the logic in two places,
consolidate the logic in the display manager.

Acked-by: default avatarYifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fd546bc5

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

+3 −27
Original line number Diff line number Diff line
@@ -506,33 +506,9 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, 
	 */

	if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&

	    amdgpu_bo_support_uswc(bo_flags) &&

	    amdgpu_device_asic_has_dc_support(adev->asic_type)) {

		switch (adev->asic_type) {

		case CHIP_CARRIZO:

		case CHIP_STONEY:

	    amdgpu_device_asic_has_dc_support(adev->asic_type) &&

	    adev->mode_info.gpu_vm_support)

		domain |= AMDGPU_GEM_DOMAIN_GTT;

			break;

		default:

			switch (adev->ip_versions[DCE_HWIP][0]) {

			case IP_VERSION(1, 0, 0):

			case IP_VERSION(1, 0, 1):

				/* enable S/G on PCO and RV2 */

				if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||

				    (adev->apu_flags & AMD_APU_IS_PICASSO))

					domain |= AMDGPU_GEM_DOMAIN_GTT;

				break;

			case IP_VERSION(2, 1, 0):

			case IP_VERSION(3, 0, 1):

			case IP_VERSION(3, 1, 2):

			case IP_VERSION(3, 1, 3):

				domain |= AMDGPU_GEM_DOMAIN_GTT;

				break;

			default:

				break;

			}

			break;

		}

	}

#endif



	return domain;

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

+1 −0
Original line number Diff line number Diff line
@@ -341,6 +341,7 @@ struct amdgpu_mode_info { 
	int			num_crtc; /* number of crtcs */

	int			num_hpd; /* number of hpd pins */

	int			num_dig; /* number of dig blocks */

	bool			gpu_vm_support; /* supports display from GTT */

	int			disp_priority;

	const struct amdgpu_display_funcs *funcs;

	const enum drm_plane_type *plane_type;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+8 −0
Original line number Diff line number Diff line
@@ -1471,6 +1471,11 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) 
		switch (adev->ip_versions[DCE_HWIP][0]) {

		case IP_VERSION(1, 0, 0):

		case IP_VERSION(1, 0, 1):

			/* enable S/G on PCO and RV2 */

			if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||

			    (adev->apu_flags & AMD_APU_IS_PICASSO))

				init_data.flags.gpu_vm_support = true;

			break;

		case IP_VERSION(2, 1, 0):

		case IP_VERSION(3, 0, 1):

		case IP_VERSION(3, 1, 2):
@@ -1484,6 +1489,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) 
		break;

	}



	if (init_data.flags.gpu_vm_support)

		adev->mode_info.gpu_vm_support = true;



	if (amdgpu_dc_feature_mask & DC_FBC_MASK)

		init_data.flags.fbc_support = true;