Commit a5aedc2d authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
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drm/amdgpu: reduce the idle period that RLC has to wait before request CGCG 



Gfxoff feature may depends on the CGCG(on vega12, that's the case). This
change will help to enable gfxoff feature more frequently.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c3693768

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+7 −4
Original line number Diff line number Diff line
@@ -3632,9 +3632,11 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 
		/* update CGCG and CGLS override bits */

		if (def != data)

			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);

		/* enable 3Dcgcg FSM(0x0020003f) */



		/* enable 3Dcgcg FSM(0x0000363f) */

		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);

		data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |



		data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |

			RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;

		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)

			data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
@@ -3681,9 +3683,10 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev 
		if (def != data)

			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);



		/* enable cgcg FSM(0x0020003F) */

		/* enable cgcg FSM(0x0000363F) */

		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);

		data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |



		data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |

			RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;

		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)

			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |