Commit a499e40a authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
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ARM: dts: renesas: Move enable-method to CPU nodes 



According to Documentation/devicetree/bindings/arm/cpus.yaml, the
"enable-method" property should be a property of the individual CPU
nodes, and not of the parent "cpus" container node.
However, on R-Car Gen2 and RZ/G1 SoCs, the property is tied to the
"cpus" node instead.

Secondary CPU bringup and CPU hot (un)plug work regardless, as
arm_dt_init_cpu_maps() falls back to looking in the "cpus" node.

The cpuidle code does not have such a fallback, so it does not detect
the enable-method.  Note that cpuidle does not support the
"renesas,apmu" enable-method yet, so for now this does not make any
difference.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/35fcfedf9de9269185c48ca5a6dfcba7cdd3484b.1621427319.git.geert+renesas@glider.be
parent ebc666f3

arch/arm/boot/dts/r8a7742.dtsi

+4 −1
Original line number Diff line number Diff line
@@ -47,7 +47,6 @@ can_clk: can { 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "renesas,apmu";



		cpu0: cpu@0 {

			device_type = "cpu";
@@ -56,6 +55,7 @@ cpu0: cpu@0 { 
			clock-frequency = <1400000000>;

			clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;

			power-domains = <&sysc R8A7742_PD_CA15_CPU0>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA15>;

			capacity-dmips-mhz = <1024>;

			voltage-tolerance = <1>; /* 1% */
@@ -77,6 +77,7 @@ cpu1: cpu@1 { 
			clock-frequency = <1400000000>;

			clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;

			power-domains = <&sysc R8A7742_PD_CA15_CPU1>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA15>;

			capacity-dmips-mhz = <1024>;

			voltage-tolerance = <1>; /* 1% */
@@ -98,6 +99,7 @@ cpu2: cpu@2 { 
			clock-frequency = <1400000000>;

			clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;

			power-domains = <&sysc R8A7742_PD_CA15_CPU2>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA15>;

			capacity-dmips-mhz = <1024>;

			voltage-tolerance = <1>; /* 1% */
@@ -119,6 +121,7 @@ cpu3: cpu@3 { 
			clock-frequency = <1400000000>;

			clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;

			power-domains = <&sysc R8A7742_PD_CA15_CPU3>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA15>;

			capacity-dmips-mhz = <1024>;

			voltage-tolerance = <1>; /* 1% */

arch/arm/boot/dts/r8a7743.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -49,7 +49,6 @@ can_clk: can { 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "renesas,apmu";



		cpu0: cpu@0 {

			device_type = "cpu";
@@ -59,6 +58,7 @@ cpu0: cpu@0 { 
			clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;

			clock-latency = <300000>; /* 300 us */

			power-domains = <&sysc R8A7743_PD_CA15_CPU0>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA15>;



			/* kHz - uV - OPPs unknown yet */
@@ -78,6 +78,7 @@ cpu1: cpu@1 { 
			clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;

			clock-latency = <300000>; /* 300 us */

			power-domains = <&sysc R8A7743_PD_CA15_CPU1>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA15>;



			/* kHz - uV - OPPs unknown yet */

arch/arm/boot/dts/r8a7744.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -49,7 +49,6 @@ can_clk: can { 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "renesas,apmu";



		cpu0: cpu@0 {

			device_type = "cpu";
@@ -59,6 +58,7 @@ cpu0: cpu@0 { 
			clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;

			clock-latency = <300000>; /* 300 us */

			power-domains = <&sysc R8A7744_PD_CA15_CPU0>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA15>;



			/* kHz - uV - OPPs unknown yet */
@@ -78,6 +78,7 @@ cpu1: cpu@1 { 
			clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;

			clock-latency = <300000>; /* 300 us */

			power-domains = <&sysc R8A7744_PD_CA15_CPU1>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA15>;



			/* kHz - uV - OPPs unknown yet */

arch/arm/boot/dts/r8a7745.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -64,7 +64,6 @@ can_clk: can { 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "renesas,apmu";



		cpu0: cpu@0 {

			device_type = "cpu";
@@ -73,6 +72,7 @@ cpu0: cpu@0 { 
			clock-frequency = <1000000000>;

			clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;

			power-domains = <&sysc R8A7745_PD_CA7_CPU0>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA7>;

		};
@@ -83,6 +83,7 @@ cpu1: cpu@1 { 
			clock-frequency = <1000000000>;

			clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;

			power-domains = <&sysc R8A7745_PD_CA7_CPU1>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA7>;

		};

arch/arm/boot/dts/r8a77470.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -25,7 +25,6 @@ aliases { 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "renesas,apmu";



		cpu0: cpu@0 {

			device_type = "cpu";
@@ -34,6 +33,7 @@ cpu0: cpu@0 { 
			clock-frequency = <1000000000>;

			clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;

			power-domains = <&sysc R8A77470_PD_CA7_CPU0>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA7>;

		};
@@ -44,6 +44,7 @@ cpu1: cpu@1 { 
			clock-frequency = <1000000000>;

			clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;

			power-domains = <&sysc R8A77470_PD_CA7_CPU1>;

			enable-method = "renesas,apmu";

			next-level-cache = <&L2_CA7>;

		};