Commit a2efebf1 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/discovery: store the number of UMC IPs on the asic 



For chips with IP discovery get this from the table,
hardcode it for older asics.

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 053d35de

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+9 −0
Original line number Diff line number Diff line
@@ -1033,6 +1033,9 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 
			    le16_to_cpu(ip->hw_id) == SDMA3_HWID)

				adev->sdma.num_instances++;



			if (le16_to_cpu(ip->hw_id) == UMC_HWID)

				adev->gmc.num_umc++;



			for (k = 0; k < num_base_address; k++) {

				/*

				 * convert the endianness of base addresses in place,
@@ -1667,6 +1670,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	case CHIP_VEGA10:

		vega10_reg_base_init(adev);

		adev->sdma.num_instances = 2;

		adev->gmc.num_umc = 4;

		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);

		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);

		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
@@ -1688,6 +1692,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	case CHIP_VEGA12:

		vega10_reg_base_init(adev);

		adev->sdma.num_instances = 2;

		adev->gmc.num_umc = 4;

		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);

		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);

		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
@@ -1710,6 +1715,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
		vega10_reg_base_init(adev);

		adev->sdma.num_instances = 1;

		adev->vcn.num_vcn_inst = 1;

		adev->gmc.num_umc = 2;

		if (adev->apu_flags & AMD_APU_IS_RAVEN2) {

			adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);

			adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
@@ -1747,6 +1753,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	case CHIP_VEGA20:

		vega20_reg_base_init(adev);

		adev->sdma.num_instances = 2;

		adev->gmc.num_umc = 8;

		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);

		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);

		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
@@ -1770,6 +1777,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
		arct_reg_base_init(adev);

		adev->sdma.num_instances = 8;

		adev->vcn.num_vcn_inst = 2;

		adev->gmc.num_umc = 8;

		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);

		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);

		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
@@ -1797,6 +1805,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
		aldebaran_reg_base_init(adev);

		adev->sdma.num_instances = 5;

		adev->vcn.num_vcn_inst = 2;

		adev->gmc.num_umc = 4;

		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);

		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);

		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

+2 −0
Original line number Diff line number Diff line
@@ -260,6 +260,8 @@ struct amdgpu_gmc { 


	/* MALL size */

	u64 mall_size;

	/* number of UMC instances */

	int num_umc;

};



#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))