Commit a2475e62 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/display: correct asic type check V2 



Check chip family also to avoid wrong identification.

V2: use the correct macro without AMDGPU prefix

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b1878847

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

+4 −2
Original line number Diff line number Diff line
@@ -736,10 +736,11 @@ static void hack_bounding_box(struct dcn_bw_internal_vars *v, 
		hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);

}



unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev, uint32_t pci_revision_id)

unsigned int get_highest_allowed_voltage_level(uint32_t chip_family, uint32_t hw_internal_rev, uint32_t pci_revision_id)

{

	/* for low power RV2 variants, the highest voltage level we want is 0 */

	if (ASICREV_IS_RAVEN2(hw_internal_rev))

	if ((chip_family == FAMILY_RV) &&

	     ASICREV_IS_RAVEN2(hw_internal_rev))

		switch (pci_revision_id) {

		case PRID_DALI_DE:

		case PRID_DALI_DF:
@@ -1324,6 +1325,7 @@ bool dcn_validate_bandwidth( 
	BW_VAL_TRACE_FINISH();



	if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(

							dc->ctx->asic_id.chip_family,

							dc->ctx->asic_id.hw_internal_rev,

							dc->ctx->asic_id.pci_revision_id))

		return true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

+2 −1
Original line number Diff line number Diff line
@@ -195,7 +195,8 @@ void dce11_pplib_apply_display_requirements( 
	 * , then change minimum memory clock based on real-time bandwidth

	 * limitation.

	 */

	if (ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) {

	if ((dc->ctx->asic_id.chip_family == FAMILY_AI) &&

	     ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) {

		pp_display_cfg->min_memory_clock_khz = max(pp_display_cfg->min_memory_clock_khz,

							   (uint32_t) div64_s64(

								   div64_s64(dc->bw_vbios->high_yclk.value,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

+5 −2
Original line number Diff line number Diff line
@@ -100,7 +100,9 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) 
	/*VBIOS will determine DPREFCLK frequency, so we don't set it*/

	dce_clk_params.target_clock_frequency = 0;

	dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;

	if (!ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))



	if (!((clk_mgr_base->ctx->asic_id.chip_family == FAMILY_AI) &&

	       ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)))

		dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =

			(dce_clk_params.pll_id ==

					CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
@@ -176,7 +178,8 @@ int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr) 
	dce_clk_params.target_clock_frequency = 0;

	dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;

	dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;

	if (!ASICREV_IS_VEGA20_P(clk_mgr->base.ctx->asic_id.hw_internal_rev))

	if (!((clk_mgr->base.ctx->asic_id.chip_family == FAMILY_AI) &&

	       ASICREV_IS_VEGA20_P(clk_mgr->base.ctx->asic_id.hw_internal_rev)))

		dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =

			(dce_clk_params.pll_id ==

					CLOCK_SOURCE_COMBO_DISPLAY_PLL0);

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+2 −1
Original line number Diff line number Diff line
@@ -2732,7 +2732,8 @@ bool dc_link_setup_psr(struct dc_link *link, 


#if defined(CONFIG_DRM_AMD_DC_DCN)

	/*skip power down the single pipe since it blocks the cstate*/

	if (ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))

	if ((link->ctx->asic_id.chip_family == FAMILY_AI) &&

	     ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))

		psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;

#endif

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

+3 −1
Original line number Diff line number Diff line
@@ -317,7 +317,9 @@ int dce112_set_clock(struct clk_mgr *clk_mgr, int requested_clk_khz) 
	/*VBIOS will determine DPREFCLK frequency, so we don't set it*/

	dce_clk_params.target_clock_frequency = 0;

	dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;

	if (!ASICREV_IS_VEGA20_P(clk_mgr->ctx->asic_id.hw_internal_rev))



	if (!((clk_mgr->ctx->asic_id.chip_family == FAMILY_AI) &&

	       ASICREV_IS_VEGA20_P(clk_mgr->ctx->asic_id.hw_internal_rev)))

		dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =

			(dce_clk_params.pll_id ==

					CLOCK_SOURCE_COMBO_DISPLAY_PLL0);