Commit 9dca4435 authored by Shukun Tan's avatar Shukun Tan Committed by Herbert Xu
Browse files

crypto: hisilicon/qm - fix event queue depth to 2048 



Increasing depth of 'event queue' from 1024 to 2048, which equals to twice
depth of 'completion queue'. It will fix the easily happened 'event queue
overflow' as using 1024 queue depth for 'event queue'.

Fixes: 263c9959("crypto: hisilicon - add queue management driver...")
Signed-off-by: default avatarShukun Tan <tanshukun1@huawei.com>
Signed-off-by: default avatarYang Shen <shenyang39@huawei.com>
Reviewed-by: default avatarZhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 71d1ca49

drivers/crypto/hisilicon/qm.c

+13 −6
Original line number Diff line number Diff line
@@ -181,6 +181,7 @@ 
#define QM_PCI_COMMAND_INVALID		~0



#define QM_SQE_ADDR_MASK		GENMASK(7, 0)

#define QM_EQ_DEPTH			(1024 * 2)



#define QM_MK_CQC_DW3_V1(hop_num, pg_sz, buf_sz, cqe_sz) \

	(((hop_num) << QM_CQ_HOP_NUM_SHIFT)	| \
@@ -652,7 +653,7 @@ static void qm_work_process(struct work_struct *work) 
		qp = qm_to_hisi_qp(qm, eqe);

		qm_poll_qp(qp, qm);



		if (qm->status.eq_head == QM_Q_DEPTH - 1) {

		if (qm->status.eq_head == QM_EQ_DEPTH - 1) {

			qm->status.eqc_phase = !qm->status.eqc_phase;

			eqe = qm->eqe;

			qm->status.eq_head = 0;
@@ -661,7 +662,7 @@ static void qm_work_process(struct work_struct *work) 
			qm->status.eq_head++;

		}



		if (eqe_num == QM_Q_DEPTH / 2 - 1) {

		if (eqe_num == QM_EQ_DEPTH / 2 - 1) {

			eqe_num = 0;

			qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);

		}
@@ -1371,7 +1372,13 @@ static int qm_eq_aeq_dump(struct hisi_qm *qm, const char *s, 
		return -EINVAL;



	ret = kstrtou32(s, 0, &xeqe_id);

	if (ret || xeqe_id >= QM_Q_DEPTH) {

	if (ret)

		return -EINVAL;



	if (!strcmp(name, "EQE") && xeqe_id >= QM_EQ_DEPTH) {

		dev_err(dev, "Please input eqe num (0-%d)", QM_EQ_DEPTH - 1);

		return -EINVAL;

	} else if (!strcmp(name, "AEQE") && xeqe_id >= QM_Q_DEPTH) {

		dev_err(dev, "Please input aeqe num (0-%d)", QM_Q_DEPTH - 1);

		return -EINVAL;

	}
@@ -2285,7 +2292,7 @@ static int hisi_qm_memory_init(struct hisi_qm *qm) 
} while (0)



	idr_init(&qm->qp_idr);

	qm->qdma.size = QMC_ALIGN(sizeof(struct qm_eqe) * QM_Q_DEPTH) +

	qm->qdma.size = QMC_ALIGN(sizeof(struct qm_eqe) * QM_EQ_DEPTH) +

			QMC_ALIGN(sizeof(struct qm_aeqe) * QM_Q_DEPTH) +

			QMC_ALIGN(sizeof(struct qm_sqc) * qm->qp_num) +

			QMC_ALIGN(sizeof(struct qm_cqc) * qm->qp_num);
@@ -2295,7 +2302,7 @@ static int hisi_qm_memory_init(struct hisi_qm *qm) 
	if (!qm->qdma.va)

		return -ENOMEM;



	QM_INIT_BUF(qm, eqe, QM_Q_DEPTH);

	QM_INIT_BUF(qm, eqe, QM_EQ_DEPTH);

	QM_INIT_BUF(qm, aeqe, QM_Q_DEPTH);

	QM_INIT_BUF(qm, sqc, qm->qp_num);

	QM_INIT_BUF(qm, cqc, qm->qp_num);
@@ -2465,7 +2472,7 @@ static int qm_eq_ctx_cfg(struct hisi_qm *qm) 
	eqc->base_h = cpu_to_le32(upper_32_bits(qm->eqe_dma));

	if (qm->ver == QM_HW_V1)

		eqc->dw3 = cpu_to_le32(QM_EQE_AEQE_SIZE);

	eqc->dw6 = cpu_to_le32((QM_Q_DEPTH - 1) | (1 << QM_EQC_PHASE_SHIFT));

	eqc->dw6 = cpu_to_le32((QM_EQ_DEPTH - 1) | (1 << QM_EQC_PHASE_SHIFT));

	ret = qm_mb(qm, QM_MB_CMD_EQC, eqc_dma, 0, 0);

	dma_unmap_single(dev, eqc_dma, sizeof(struct qm_eqc), DMA_TO_DEVICE);

	kfree(eqc);