ARM: EXYNOS4: Add PMU register definition for EXYNOS4212

#define S5P_USE_STANDBY_WFI0			(1 << 16)

#define S5P_USE_STANDBY_WFI1			(1 << 17)

#define S5P_USE_STANDBYWFI_ISP_ARM		(1 << 18)

#define S5P_USE_STANDBY_WFE0			(1 << 24)

#define S5P_USE_STANDBY_WFE1			(1 << 25)

#define S5P_USE_STANDBYWFE_ISP_ARM		(1 << 26)

#define S5P_SWRESET				S5P_PMUREG(0x0400)

#define S5P_HDMI_PHY_CONTROL			S5P_PMUREG(0x0700)

#define S5P_HDMI_PHY_ENABLE			(1 << 0)

#define S5P_USBHOST_PHY_CONTROL			S5P_PMUREG(0x0708)

#define S5P_USBHOST_PHY_ENABLE			(1 << 0)

#define S5P_DAC_PHY_CONTROL			S5P_PMUREG(0x070C)

#define S5P_DAC_PHY_ENABLE			(1 << 0)

#define S5P_MIPI_DPHY_SRESETN			(1 << 1)

#define S5P_MIPI_DPHY_MRESETN			(1 << 2)

#define S5P_PMU_SATA_PHY_CONTROL		S5P_PMUREG(0x0720)

#define S5P_INFORM0				S5P_PMUREG(0x0800)

#define S5P_INFORM1				S5P_PMUREG(0x0804)

#define S5P_INFORM2				S5P_PMUREG(0x0808)

#define S5P_CMU_CLKSTOP_MFC_LOWPWR		S5P_PMUREG(0x1148)

#define S5P_CMU_CLKSTOP_G3D_LOWPWR		S5P_PMUREG(0x114C)

#define S5P_CMU_CLKSTOP_LCD0_LOWPWR		S5P_PMUREG(0x1150)

#define S5P_CMU_CLKSTOP_LCD1_LOWPWR		S5P_PMUREG(0x1154)

#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR		S5P_PMUREG(0x1158)

#define S5P_CMU_CLKSTOP_GPS_LOWPWR		S5P_PMUREG(0x115C)

#define S5P_CMU_RESET_CAM_LOWPWR		S5P_PMUREG(0x1160)

#define S5P_CMU_RESET_MFC_LOWPWR		S5P_PMUREG(0x1168)

#define S5P_CMU_RESET_G3D_LOWPWR		S5P_PMUREG(0x116C)

#define S5P_CMU_RESET_LCD0_LOWPWR		S5P_PMUREG(0x1170)

#define S5P_CMU_RESET_LCD1_LOWPWR		S5P_PMUREG(0x1174)

#define S5P_CMU_RESET_MAUDIO_LOWPWR		S5P_PMUREG(0x1178)

#define S5P_CMU_RESET_GPS_LOWPWR		S5P_PMUREG(0x117C)

#define S5P_TOP_BUS_LOWPWR			S5P_PMUREG(0x1180)

#define S5P_TOP_PWR_LOWPWR			S5P_PMUREG(0x1188)

#define S5P_LOGIC_RESET_LOWPWR			S5P_PMUREG(0x11A0)

#define S5P_ONENAND_MEM_LOWPWR			S5P_PMUREG(0x11C0)

#define S5P_MODIMIF_MEM_LOWPWR			S5P_PMUREG(0x11C4)

#define S5P_G2D_ACP_MEM_LOWPWR			S5P_PMUREG(0x11C8)

#define S5P_USBOTG_MEM_LOWPWR			S5P_PMUREG(0x11CC)

#define S5P_HSMMC_MEM_LOWPWR			S5P_PMUREG(0x11D0)

#define S5P_CSSYS_MEM_LOWPWR			S5P_PMUREG(0x11D4)

#define S5P_SECSS_MEM_LOWPWR			S5P_PMUREG(0x11D8)

#define S5P_PCIE_MEM_LOWPWR			S5P_PMUREG(0x11E0)

#define S5P_SATA_MEM_LOWPWR			S5P_PMUREG(0x11E4)

#define S5P_PAD_RETENTION_DRAM_LOWPWR		S5P_PMUREG(0x1200)

#define S5P_PAD_RETENTION_MAUDIO_LOWPWR		S5P_PMUREG(0x1204)

#define S5P_PAD_RETENTION_GPIO_LOWPWR		S5P_PMUREG(0x1220)

#define S5P_MFC_LOWPWR				S5P_PMUREG(0x1388)

#define S5P_G3D_LOWPWR				S5P_PMUREG(0x138C)

#define S5P_LCD0_LOWPWR				S5P_PMUREG(0x1390)

#define S5P_LCD1_LOWPWR				S5P_PMUREG(0x1394)

#define S5P_MAUDIO_LOWPWR			S5P_PMUREG(0x1398)

#define S5P_GPS_LOWPWR				S5P_PMUREG(0x139C)

#define S5P_GPS_ALIVE_LOWPWR			S5P_PMUREG(0x13A0)

#define S5P_PMU_MFC_CONF			S5P_PMUREG(0x3C40)

#define S5P_PMU_G3D_CONF			S5P_PMUREG(0x3C60)

#define S5P_PMU_LCD0_CONF			S5P_PMUREG(0x3C80)

#define S5P_PMU_LCD1_CONF			S5P_PMUREG(0x3CA0)

#define S5P_PMU_GPS_CONF			S5P_PMUREG(0x3CE0)

#define S5P_PMU_SATA_PHY_CONTROL_EN		0x1

#define S5P_CHECK_SLEEP				0x00000BAD

/* Only for EXYNOS4210 */

#define S5P_USBHOST_PHY_CONTROL		S5P_PMUREG(0x0708)

#define S5P_USBHOST_PHY_ENABLE		(1 << 0)

#define S5P_PMU_SATA_PHY_CONTROL	S5P_PMUREG(0x0720)

#define S5P_CMU_CLKSTOP_LCD1_LOWPWR	S5P_PMUREG(0x1154)

#define S5P_CMU_RESET_LCD1_LOWPWR	S5P_PMUREG(0x1174)

#define S5P_MODIMIF_MEM_LOWPWR		S5P_PMUREG(0x11C4)

#define S5P_PCIE_MEM_LOWPWR		S5P_PMUREG(0x11E0)

#define S5P_SATA_MEM_LOWPWR		S5P_PMUREG(0x11E4)

#define S5P_LCD1_LOWPWR			S5P_PMUREG(0x1394)

#define S5P_PMU_LCD1_CONF		S5P_PMUREG(0x3CA0)

/* Only for EXYNOS4212 */

#define S5P_ISP_ARM_LOWPWR			S5P_PMUREG(0x1050)

#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR	S5P_PMUREG(0x1054)

#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR	S5P_PMUREG(0x1058)

#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR		S5P_PMUREG(0x1110)

#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR		S5P_PMUREG(0x1114)

#define S5P_CMU_RESET_COREBLK_LOWPWR		S5P_PMUREG(0x111C)

#define S5P_MPLLUSER_SYSCLK_LOWPWR		S5P_PMUREG(0x1130)

#define S5P_CMU_CLKSTOP_ISP_LOWPWR		S5P_PMUREG(0x1154)

#define S5P_CMU_RESET_ISP_LOWPWR		S5P_PMUREG(0x1174)

#define S5P_TOP_BUS_COREBLK_LOWPWR		S5P_PMUREG(0x1190)

#define S5P_TOP_RETENTION_COREBLK_LOWPWR	S5P_PMUREG(0x1194)

#define S5P_TOP_PWR_COREBLK_LOWPWR		S5P_PMUREG(0x1198)

#define S5P_OSCCLK_GATE_LOWPWR			S5P_PMUREG(0x11A4)

#define S5P_LOGIC_RESET_COREBLK_LOWPWR		S5P_PMUREG(0x11B0)

#define S5P_OSCCLK_GATE_COREBLK_LOWPWR		S5P_PMUREG(0x11B4)

#define S5P_HSI_MEM_LOWPWR			S5P_PMUREG(0x11C4)

#define S5P_ROTATOR_MEM_LOWPWR			S5P_PMUREG(0x11DC)

#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR	S5P_PMUREG(0x123C)

#define S5P_PAD_ISOLATION_COREBLK_LOWPWR	S5P_PMUREG(0x1250)

#define S5P_GPIO_MODE_COREBLK_LOWPWR		S5P_PMUREG(0x1320)

#define S5P_TOP_ASB_RESET_LOWPWR		S5P_PMUREG(0x1344)

#define S5P_TOP_ASB_ISOLATION_LOWPWR		S5P_PMUREG(0x1348)

#define S5P_ISP_LOWPWR				S5P_PMUREG(0x1394)

#define S5P_DRAM_FREQ_DOWN_LOWPWR		S5P_PMUREG(0x13B0)

#define S5P_DDRPHY_DLLOFF_LOWPWR		S5P_PMUREG(0x13B4)

#define S5P_CMU_SYSCLK_ISP_LOWPWR		S5P_PMUREG(0x13B8)

#define S5P_CMU_SYSCLK_GPS_LOWPWR		S5P_PMUREG(0x13BC)

#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR		S5P_PMUREG(0x13C0)

#define S5P_ARM_L2_0_OPTION			S5P_PMUREG(0x2608)

#define S5P_ARM_L2_1_OPTION			S5P_PMUREG(0x2628)

#define S5P_ONENAND_MEM_OPTION			S5P_PMUREG(0x2E08)

#define S5P_HSI_MEM_OPTION			S5P_PMUREG(0x2E28)

#define S5P_G2D_ACP_MEM_OPTION			S5P_PMUREG(0x2E48)

#define S5P_USBOTG_MEM_OPTION			S5P_PMUREG(0x2E68)

#define S5P_HSMMC_MEM_OPTION			S5P_PMUREG(0x2E88)

#define S5P_CSSYS_MEM_OPTION			S5P_PMUREG(0x2EA8)

#define S5P_SECSS_MEM_OPTION			S5P_PMUREG(0x2EC8)

#define S5P_ROTATOR_MEM_OPTION			S5P_PMUREG(0x2F48)

#endif /* __ASM_ARCH_REGS_PMU_H */