Commit 989e7e35 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'imx-dt64-5.14' of... 

Merge tag 'imx-dt64-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm64 device tree chagnes for 5.14:

- New board support: i.MX8MM Gateworks GW7901 board.
- Add SPBA bus description for i.MX8MN and i.MX8MM.
- A series of update on imx8mq-nitrogen board to add USB OTG/Host and
  LT8912 MIPI-DSI to HDMI support.
- Correct enet clock description for i.MX8 Connection Subsystem.
- A couple of patches from Heiko Schocher to add FlexSPI device for
  i.MX8MP SoC and enable SPI NOR Flash support on imx8mp-phycore-som.
- Remove the reference to audio IPG clock on i.MX8MP.
- Enable EQOS Ethernet and PMIC device support for imx8mp-evk.
- Disable USB over-current on imx8mm-evk and imx8mn-evk.
- Add dma-ranges description for i.MX8MM and i.MX8MN SoC.
- Add PCIe clock description for i.MX8MQ SoC.
- Enable PCIe support on freeway board.
- Enable OPTEE support on ls1028a-rdb board.

* tag 'imx-dt64-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (24 commits)
  arm64: dts: imx8mn-evk: disable over current for usb
  arm64: dts: imx8mm-evk: disable over current for usb1
  arm64: dts: freescale: Separate each group of data in the property 'reg'
  arm64: dts: imx8: conn: fix enet clock setting
  arm64: dts: imx8mq: assign PCIe clocks
  arm64: dts: imx8mn: specify dma-ranges
  arm64: dts: imx8mm: specify dma-ranges
  arm64: dts: fsl-ls1028a: Correct ECAM PCIE window ranges
  arm64: dts: imx8mn-beacon-som: Assign PMIC clock
  arm64: dts: ls208xa: remove bus-num from dspi node
  arm64: dts: ls1012a: enable PCIe on freeway board
  arm64: dts: imx8mp-evk: enable EQOS ethernet
  arm64: dts: imx8mp: Remove the reference to audio ipg clock on imx8mp
  arm64: dts: imx8mq-evk: add one regulator used to power up pcie phy
  arm64: dts: imx8mm: Add spba1 and spba2 buses
  arm64: dts: imx8mn: Add spba1 bus
  arm64: dts: imx8mq-nitrogen: add lt8912 MIPI-DSI to HDMI
  arm64: dts: imx8mq-nitrogen: add USB HOST support
  arm64: dts: imx8mq-nitrogen: add USB OTG support
  arm64: dts: imx8mp-phycore-som: enable spi nor
  ...

Link: https://lore.kernel.org/r/20210613082544.16067-5-shawnguo@kernel.org


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 970d180b 21cc1f22

arch/arm64/boot/dts/freescale/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb 
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb

arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts

+4 −0
Original line number Diff line number Diff line
@@ -24,6 +24,10 @@ &i2c0 { 
	status = "okay";

};



&pcie1 {

	status = "okay";

};



&qspi {

	status = "okay";

arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi

+7 −7
Original line number Diff line number Diff line
@@ -238,35 +238,35 @@ rtic@60000 { 
					     "fsl,sec-v4.0-rtic";

				#address-cells = <1>;

				#size-cells = <1>;

				reg = <0x60000 0x100 0x60e00 0x18>;

				reg = <0x60000 0x100>, <0x60e00 0x18>;

				ranges = <0x0 0x60100 0x500>;



				rtic_a: rtic-a@0 {

					compatible = "fsl,sec-v5.4-rtic-memory",

						     "fsl,sec-v5.0-rtic-memory",

						     "fsl,sec-v4.0-rtic-memory";

					reg = <0x00 0x20 0x100 0x100>;

					reg = <0x00 0x20>, <0x100 0x100>;

				};



				rtic_b: rtic-b@20 {

					compatible = "fsl,sec-v5.4-rtic-memory",

						     "fsl,sec-v5.0-rtic-memory",

						     "fsl,sec-v4.0-rtic-memory";

					reg = <0x20 0x20 0x200 0x100>;

					reg = <0x20 0x20>, <0x200 0x100>;

				};



				rtic_c: rtic-c@40 {

					compatible = "fsl,sec-v5.4-rtic-memory",

						     "fsl,sec-v5.0-rtic-memory",

						     "fsl,sec-v4.0-rtic-memory";

					reg = <0x40 0x20 0x300 0x100>;

					reg = <0x40 0x20>, <0x300 0x100>;

				};



				rtic_d: rtic-d@60 {

					compatible = "fsl,sec-v5.4-rtic-memory",

						     "fsl,sec-v5.0-rtic-memory",

						     "fsl,sec-v4.0-rtic-memory";

					reg = <0x60 0x20 0x400 0x100>;

					reg = <0x60 0x20>, <0x400 0x100>;

				};

			};

		};
@@ -522,8 +522,8 @@ msi: msi-controller1@1572000 { 


		pcie1: pcie@3400000 {

			compatible = "fsl,ls1012a-pcie";

			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */

			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */

			reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */

			      <0x40 0x00000000 0x0 0x00002000>; /* configuration space */

			reg-names = "regs", "config";

			interrupts = <0 118 0x4>, /* controller interrupt */

				     <0 117 0x4>; /* PME interrupt */

arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts

+4 −0
Original line number Diff line number Diff line
@@ -275,6 +275,10 @@ &mscc_felix_port4 { 
	status = "okay";

};



&optee {

	status = "okay";

};



&sai4 {

	status = "okay";

};

arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

+12 −12
Original line number Diff line number Diff line
@@ -88,7 +88,7 @@ dpclk: clock-controller@f1f0000 { 
	};



	firmware {

		optee {

		optee: optee  {

			compatible = "linaro,optee-tz";

			method = "smc";

			status = "disabled";
@@ -617,8 +617,8 @@ sata: sata@3200000 { 


		pcie1: pcie@3400000 {

			compatible = "fsl,ls1028a-pcie";

			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */

			       0x80 0x00000000 0x0 0x00002000>; /* configuration space */

			reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */

			      <0x80 0x00000000 0x0 0x00002000>; /* configuration space */

			reg-names = "regs", "config";

			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */

				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
@@ -644,8 +644,8 @@ pcie1: pcie@3400000 { 


		pcie2: pcie@3500000 {

			compatible = "fsl,ls1028a-pcie";

			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */

			       0x88 0x00000000 0x0 0x00002000>; /* configuration space */

			reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */

			      <0x88 0x00000000 0x0 0x00002000>; /* configuration space */

			reg-names = "regs", "config";

			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
@@ -990,19 +990,19 @@ pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 
			msi-map = <0 &its 0x17 0xe>;

			iommu-map = <0 &smmu 0x17 0xe>;

				  /* PF0-6 BAR0 - non-prefetchable memory */

			ranges = <0x82000000 0x0 0x00000000  0x1 0xf8000000  0x0 0x160000

			ranges = <0x82000000 0x1 0xf8000000  0x1 0xf8000000  0x0 0x160000

				  /* PF0-6 BAR2 - prefetchable memory */

				  0xc2000000 0x0 0x00000000  0x1 0xf8160000  0x0 0x070000

				  0xc2000000 0x1 0xf8160000  0x1 0xf8160000  0x0 0x070000

				  /* PF0: VF0-1 BAR0 - non-prefetchable memory */

				  0x82000000 0x0 0x00000000  0x1 0xf81d0000  0x0 0x020000

				  0x82000000 0x1 0xf81d0000  0x1 0xf81d0000  0x0 0x020000

				  /* PF0: VF0-1 BAR2 - prefetchable memory */

				  0xc2000000 0x0 0x00000000  0x1 0xf81f0000  0x0 0x020000

				  0xc2000000 0x1 0xf81f0000  0x1 0xf81f0000  0x0 0x020000

				  /* PF1: VF0-1 BAR0 - non-prefetchable memory */

				  0x82000000 0x0 0x00000000  0x1 0xf8210000  0x0 0x020000

				  0x82000000 0x1 0xf8210000  0x1 0xf8210000  0x0 0x020000

				  /* PF1: VF0-1 BAR2 - prefetchable memory */

				  0xc2000000 0x0 0x00000000  0x1 0xf8230000  0x0 0x020000

				  0xc2000000 0x1 0xf8230000  0x1 0xf8230000  0x0 0x020000

				  /* BAR4 (PF5) - non-prefetchable memory */

				  0x82000000 0x0 0x00000000  0x1 0xfc000000  0x0 0x400000>;

				  0x82000000 0x1 0xfc000000  0x1 0xfc000000  0x0 0x400000>;



			enetc_port0: ethernet@0,0 {

				compatible = "fsl,enetc";