Commit 982d68b0 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: drop smu_v12_0.c unnecessary wrapper V2 



By moving the implemention to renoir_ppt.c considering
it's really ASIC specific.

V2: fix compile warnings below
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.h:40:25: warning: array subscript is above array bounds [-Warray-bounds]
    freq = table->FClocks[dpm_level].Freq; \
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:195:2: note: in expansion of macro ‘GET_DPM_CUR_FREQ’
  GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);
  ^~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.h:46:25: warning: array subscript is above array bounds [-Warray-bounds]
    freq = table->FClocks[dpm_level].Freq;  \
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:195:2: note: in expansion of macro ‘GET_DPM_CUR_FREQ’
  GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d56ff011

drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h

+0 −3
Original line number Diff line number Diff line
@@ -73,9 +73,6 @@ int smu_v12_0_set_default_dpm_tables(struct smu_context *smu); 
int smu_v12_0_get_enabled_mask(struct smu_context *smu,

				      uint32_t *feature_mask, uint32_t num);



int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,

						 uint32_t *min, uint32_t *max);



int smu_v12_0_mode2_reset(struct smu_context *smu);



int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/powerplay/renoir_ppt.c

+177 −45
Original line number Diff line number Diff line
@@ -236,23 +236,173 @@ static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type 
	if (!clk_table || clk_type >= SMU_CLK_COUNT)

		return -EINVAL;



	GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);

	switch (clk_type) {

	case SMU_SOCCLK:

		if (dpm_level >= NUM_SOCCLK_DPM_LEVELS)

			return -EINVAL;

		*freq = clk_table->SocClocks[dpm_level].Freq;

		break;

	case SMU_MCLK:

		if (dpm_level >= NUM_FCLK_DPM_LEVELS)

			return -EINVAL;

		*freq = clk_table->FClocks[dpm_level].Freq;

		break;

	case SMU_DCEFCLK:

		if (dpm_level >= NUM_DCFCLK_DPM_LEVELS)

			return -EINVAL;

		*freq = clk_table->DcfClocks[dpm_level].Freq;

		break;

	case SMU_FCLK:

		if (dpm_level >= NUM_FCLK_DPM_LEVELS)

			return -EINVAL;

		*freq = clk_table->FClocks[dpm_level].Freq;

		break;

	default:

		return -EINVAL;

	}



	return 0;

}



static int renoir_get_profiling_clk_mask(struct smu_context *smu,

					 enum amd_dpm_forced_level level,

					 uint32_t *sclk_mask,

					 uint32_t *mclk_mask,

					 uint32_t *soc_mask)

{



	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {

		if (sclk_mask)

			*sclk_mask = 0;

	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {

		if (mclk_mask)

			*mclk_mask = 0;

	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {

		if(sclk_mask)

			/* The sclk as gfxclk and has three level about max/min/current */

			*sclk_mask = 3 - 1;



		if(mclk_mask)

			*mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;



		if(soc_mask)

			*soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;

	}



	return 0;

}



static int renoir_get_dpm_ultimate_freq(struct smu_context *smu,

					enum smu_clk_type clk_type,

					uint32_t *min,

					uint32_t *max)

{

	int ret = 0;

	uint32_t mclk_mask, soc_mask;

	uint32_t clock_limit;



	if (!smu_clk_dpm_is_enabled(smu, clk_type)) {

		switch (clk_type) {

		case SMU_MCLK:

		case SMU_UCLK:

			clock_limit = smu->smu_table.boot_values.uclk;

			break;

		case SMU_GFXCLK:

		case SMU_SCLK:

			clock_limit = smu->smu_table.boot_values.gfxclk;

			break;

		case SMU_SOCCLK:

			clock_limit = smu->smu_table.boot_values.socclk;

			break;

		default:

			clock_limit = 0;

			break;

		}



		/* clock in Mhz unit */

		if (min)

			*min = clock_limit / 100;

		if (max)

			*max = clock_limit / 100;



		return 0;

	}



	if (max) {

		ret = renoir_get_profiling_clk_mask(smu,

						    AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,

						    NULL,

						    &mclk_mask,

						    &soc_mask);

		if (ret)

			goto failed;



		switch (clk_type) {

		case SMU_GFXCLK:

		case SMU_SCLK:

			ret = smu_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);

			if (ret) {

				dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n");

				goto failed;

			}

			break;

		case SMU_UCLK:

		case SMU_FCLK:

		case SMU_MCLK:

			ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);

			if (ret)

				goto failed;

			break;

		case SMU_SOCCLK:

			ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max);

			if (ret)

				goto failed;

			break;

		default:

			ret = -EINVAL;

			goto failed;

		}

	}



	if (min) {

		switch (clk_type) {

		case SMU_GFXCLK:

		case SMU_SCLK:

			ret = smu_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);

			if (ret) {

				dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n");

				goto failed;

			}

			break;

		case SMU_UCLK:

		case SMU_FCLK:

		case SMU_MCLK:

			ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);

			if (ret)

				goto failed;

			break;

		case SMU_SOCCLK:

			ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);

			if (ret)

				goto failed;

			break;

		default:

			ret = -EINVAL;

			goto failed;

		}

	}

failed:

	return ret;

}



static int renoir_print_clk_levels(struct smu_context *smu,

			enum smu_clk_type clk_type, char *buf)

{

	int i, size = 0, ret = 0;

	uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;

	DpmClocks_t *clk_table = smu->smu_table.clocks_table;

	SmuMetrics_t metrics;

	bool cur_value_match_level = false;



	if (!clk_table || clk_type >= SMU_CLK_COUNT)

		return -EINVAL;



	memset(&metrics, 0, sizeof(metrics));



	ret = renoir_get_metrics_table(smu, &metrics);
@@ -264,7 +414,7 @@ static int renoir_print_clk_levels(struct smu_context *smu, 
	case SMU_SCLK:

		/* retirve table returned paramters unit is MHz */

		cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];

		ret = smu_v12_0_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max);

		ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max);

		if (!ret) {

			/* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */

			if (cur_value  == max)
@@ -304,7 +454,9 @@ static int renoir_print_clk_levels(struct smu_context *smu, 
	}



	for (i = 0; i < count; i++) {

		GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);

		ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value);

		if (ret)

			return ret;

		if (!value)

			continue;

		size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
@@ -434,7 +586,7 @@ static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest) 


	for (i = 0; i < ARRAY_SIZE(clks); i++) {

		clk_type = clks[i];

		ret = smu_v12_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);

		ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);

		if (ret)

			return ret;
@@ -468,7 +620,7 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) { 


		clk_type = clk_feature_map[i].clk_type;



		ret = smu_v12_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);

		ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);

		if (ret)

			return ret;
@@ -552,33 +704,6 @@ static int renoir_get_workload_type(struct smu_context *smu, uint32_t profile) 
	return pplib_workload;

}



static int renoir_get_profiling_clk_mask(struct smu_context *smu,

					 enum amd_dpm_forced_level level,

					 uint32_t *sclk_mask,

					 uint32_t *mclk_mask,

					 uint32_t *soc_mask)

{



	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {

		if (sclk_mask)

			*sclk_mask = 0;

	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {

		if (mclk_mask)

			*mclk_mask = 0;

	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {

		if(sclk_mask)

			/* The sclk as gfxclk and has three level about max/min/current */

			*sclk_mask = 3 - 1;



		if(mclk_mask)

			*mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;



		if(soc_mask)

			*soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;

	}



	return 0;

}



/**

 * This interface get dpm clock table for dc
@@ -620,7 +745,6 @@ static int renoir_force_clk_levels(struct smu_context *smu, 


	int ret = 0 ;

	uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;

	DpmClocks_t *clk_table = smu->smu_table.clocks_table;



	soft_min_level = mask ? (ffs(mask) - 1) : 0;

	soft_max_level = mask ? (fls(mask) - 1) : 0;
@@ -633,7 +757,7 @@ static int renoir_force_clk_levels(struct smu_context *smu, 
			return -EINVAL;

		}



		ret = smu_v12_0_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq);

		ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq);

		if (ret)

			return ret;

		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
@@ -650,8 +774,12 @@ static int renoir_force_clk_levels(struct smu_context *smu, 
			return ret;

		break;

	case SMU_SOCCLK:

		GET_DPM_CUR_FREQ(clk_table, clk_type, soft_min_level, min_freq);

		GET_DPM_CUR_FREQ(clk_table, clk_type, soft_max_level, max_freq);

		ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);

		if (ret)

			return ret;

		ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);

		if (ret)

			return ret;

		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL);

		if (ret)

			return ret;
@@ -661,8 +789,12 @@ static int renoir_force_clk_levels(struct smu_context *smu, 
		break;

	case SMU_MCLK:

	case SMU_FCLK:

		GET_DPM_CUR_FREQ(clk_table, clk_type, soft_min_level, min_freq);

		GET_DPM_CUR_FREQ(clk_table, clk_type, soft_max_level, max_freq);

		ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);

		if (ret)

			return ret;

		ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);

		if (ret)

			return ret;

		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL);

		if (ret)

			return ret;
@@ -716,7 +848,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu) 
	int ret = 0;

	uint32_t sclk_freq = 0, uclk_freq = 0;



	ret = smu_v12_0_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq);

	ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq);

	if (ret)

		return ret;
@@ -724,7 +856,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu) 
	if (ret)

		return ret;



	ret = smu_v12_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq);

	ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq);

	if (ret)

		return ret;
@@ -961,7 +1093,7 @@ static const struct pptable_funcs renoir_ppt_funcs = { 
	.fini_smc_tables = smu_v12_0_fini_smc_tables,

	.set_default_dpm_table = smu_v12_0_set_default_dpm_tables,

	.get_enabled_mask = smu_v12_0_get_enabled_mask,

	.get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,

	.get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq,

	.mode2_reset = smu_v12_0_mode2_reset,

	.set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,

	.set_driver_table_location = smu_v12_0_set_driver_table_location,

drivers/gpu/drm/amd/powerplay/renoir_ppt.h

+0 −20
Original line number Diff line number Diff line
@@ -30,24 +30,4 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu); 
#define RENOIR_UMD_PSTATE_SOCCLK       678

#define RENOIR_UMD_PSTATE_FCLK         800



#define GET_DPM_CUR_FREQ(table, clk_type, dpm_level, freq)		\

	do {								\

		switch (clk_type) {					\

		case SMU_SOCCLK:					\

			freq = table->SocClocks[dpm_level].Freq;	\

			break;						\

		case SMU_MCLK:						\

			freq = table->FClocks[dpm_level].Freq;	\

			break;						\

		case SMU_DCEFCLK:					\

			freq = table->DcfClocks[dpm_level].Freq;	\

			break;						\

		case SMU_FCLK:						\

			freq = table->FClocks[dpm_level].Freq;		\

			break;						\

		default:						\

			break;						\

		}							\

	} while (0)



#endif

drivers/gpu/drm/amd/powerplay/smu_v12_0.c

+0 −100
Original line number Diff line number Diff line
@@ -316,106 +316,6 @@ int smu_v12_0_get_enabled_mask(struct smu_context *smu, 
	return ret;

}



int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,

						 uint32_t *min, uint32_t *max)

{

	int ret = 0;

	uint32_t mclk_mask, soc_mask;

	uint32_t clock_limit;



	if (!smu_clk_dpm_is_enabled(smu, clk_type)) {

		switch (clk_type) {

		case SMU_MCLK:

		case SMU_UCLK:

			clock_limit = smu->smu_table.boot_values.uclk;

			break;

		case SMU_GFXCLK:

		case SMU_SCLK:

			clock_limit = smu->smu_table.boot_values.gfxclk;

			break;

		case SMU_SOCCLK:

			clock_limit = smu->smu_table.boot_values.socclk;

			break;

		default:

			clock_limit = 0;

			break;

		}



		/* clock in Mhz unit */

		if (min)

			*min = clock_limit / 100;

		if (max)

			*max = clock_limit / 100;



		return 0;

	}



	if (max) {

		ret = smu_get_profiling_clk_mask(smu, AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,

						 NULL,

						 &mclk_mask,

						 &soc_mask);

		if (ret)

			goto failed;



		switch (clk_type) {

		case SMU_GFXCLK:

		case SMU_SCLK:

			ret = smu_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);

			if (ret) {

				dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n");

				goto failed;

			}

			break;

		case SMU_UCLK:

		case SMU_FCLK:

		case SMU_MCLK:

			ret = smu_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);

			if (ret)

				goto failed;

			break;

		case SMU_SOCCLK:

			ret = smu_get_dpm_clk_limited(smu, clk_type, soc_mask, max);

			if (ret)

				goto failed;

			break;

		default:

			ret = -EINVAL;

			goto failed;

		}

	}



	if (min) {

		switch (clk_type) {

		case SMU_GFXCLK:

		case SMU_SCLK:

			ret = smu_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);

			if (ret) {

				dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n");

				goto failed;

			}

			break;

		case SMU_UCLK:

		case SMU_FCLK:

		case SMU_MCLK:

			ret = smu_get_dpm_clk_limited(smu, clk_type, 0, min);

			if (ret)

				goto failed;

			break;

		case SMU_SOCCLK:

			ret = smu_get_dpm_clk_limited(smu, clk_type, 0, min);

			if (ret)

				goto failed;

			break;

		default:

			ret = -EINVAL;

			goto failed;

		}

	}

failed:

	return ret;

}



int smu_v12_0_mode2_reset(struct smu_context *smu){

	return smu_v12_0_send_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL);

}