Commit 97f40ef0 authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
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drm/amd/powerplay: Enable UVD powergating for SMU7 



This patch enables detecting VCE/UVD PG features and fixes the
UVD powergate function.

Tested on a Tonga (by reading UVD tile/clk bits during playback/idle).

Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f8991bab

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c

+9 −3
Original line number Diff line number Diff line
@@ -149,15 +149,21 @@ int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 
	if (bgate) {

		cgs_set_clockgating_state(hwmgr->device,

				AMD_IP_BLOCK_TYPE_UVD,

				AMD_CG_STATE_GATE);

				AMD_CG_STATE_UNGATE);

		cgs_set_powergating_state(hwmgr->device,

						AMD_IP_BLOCK_TYPE_UVD,

						AMD_PG_STATE_GATE);

		smu7_update_uvd_dpm(hwmgr, true);

		smu7_powerdown_uvd(hwmgr);

	} else {

		smu7_powerup_uvd(hwmgr);

		smu7_update_uvd_dpm(hwmgr, false);

		cgs_set_clockgating_state(hwmgr->device,

		cgs_set_powergating_state(hwmgr->device,

						AMD_IP_BLOCK_TYPE_UVD,

						AMD_CG_STATE_UNGATE);

		cgs_set_clockgating_state(hwmgr->device,

				AMD_IP_BLOCK_TYPE_UVD,

				AMD_CG_STATE_GATE);

		smu7_update_uvd_dpm(hwmgr, false);

	}



	return 0;

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

+14 −0
Original line number Diff line number Diff line
@@ -1352,6 +1352,8 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) 
	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);

	struct phm_ppt_v1_information *table_info =

			(struct phm_ppt_v1_information *)(hwmgr->pptable);

	struct cgs_system_info sys_info = {0};

	int result;



	data->dll_default_on = false;

	data->mclk_dpm0_activity_target = 0xa;
@@ -1439,6 +1441,18 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) 
	data->pcie_lane_performance.min = 16;

	data->pcie_lane_power_saving.max = 0;

	data->pcie_lane_power_saving.min = 16;



	sys_info.size = sizeof(struct cgs_system_info);

	sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;

	result = cgs_query_system_info(hwmgr->device, &sys_info);

	if (!result) {

		if (sys_info.value & AMD_PG_SUPPORT_UVD)

			phm_cap_set(hwmgr->platform_descriptor.platformCaps,

				      PHM_PlatformCaps_UVDPowerGating);

		if (sys_info.value & AMD_PG_SUPPORT_VCE)

			phm_cap_set(hwmgr->platform_descriptor.platformCaps,

				      PHM_PlatformCaps_VCEPowerGating);

	}

}



/**