Commit 940293af authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Tony Lindgren
Browse files

ARM: dts: dra7: Use sdhci-omap programming model



Use sdhci-omap programming model based on the generic sdhci
library for programming the eMMC/SD/SDIO controller.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 01c5d966
Loading
Loading
Loading
Loading
+2 −2
Original line number Diff line number Diff line
@@ -444,8 +444,8 @@ &mmc2 {
	vmmc-supply = <&vdd_3v3>;
	vqmmc-supply = <&vdd_3v3>;
	bus-width = <8>;
	ti,non-removable;
	cap-mmc-dual-data-rate;
	non-removable;
	no-1-8-v;
};

&sata {
+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ &mmc1 {
	pinctrl-1 = <&mmc1_pins_hs>;

	vmmc-supply = <&ldo1_reg>;
	no-1-8-v;
};

&mmc2 {
+2 −1
Original line number Diff line number Diff line
@@ -412,8 +412,9 @@ &mmc2 {
	vmmc-supply = <&v3_3d>;
	vqmmc-supply = <&v3_3d>;
	bus-width = <8>;
	ti,non-removable;
	non-removable;
	max-frequency = <96000000>;
	no-1-8-v;
};

&dcan1 {
+1 −0
Original line number Diff line number Diff line
@@ -377,6 +377,7 @@ &mmc2 {
	vmmc-supply = <&evm_1v8_sw>;
	vqmmc-supply = <&evm_1v8_sw>;
	bus-width = <8>;
	non-removable;
	pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
+10 −17
Original line number Diff line number Diff line
@@ -1079,14 +1079,10 @@ i2c5: i2c@4807c000 {
		};

		mmc1: mmc@4809c000 {
			compatible = "ti,omap4-hsmmc";
			compatible = "ti,dra7-sdhci";
			reg = <0x4809c000 0x400>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
			dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
			dma-names = "tx", "rx";
			status = "disabled";
			pbias-supply = <&pbias_mmc_reg>;
			max-frequency = <192000000>;
@@ -1100,40 +1096,37 @@ hdqw1w: 1w@480b2000 {
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap4-hsmmc";
			compatible = "ti,dra7-sdhci";
			reg = <0x480b4000 0x400>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
			dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
			dma-names = "tx", "rx";
			status = "disabled";
			max-frequency = <192000000>;
			/* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
			sdhci-caps-mask = <0x7 0x0>;
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap4-hsmmc";
			compatible = "ti,dra7-sdhci";
			reg = <0x480ad000 0x400>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
			dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
			dma-names = "tx", "rx";
			status = "disabled";
			/* Errata i887 limits max-frequency of MMC3 to 64 MHz */
			max-frequency = <64000000>;
			/* SDMA is not supported */
			sdhci-caps-mask = <0x0 0x400000>;
		};

		mmc4: mmc@480d1000 {
			compatible = "ti,omap4-hsmmc";
			compatible = "ti,dra7-sdhci";
			reg = <0x480d1000 0x400>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc4";
			ti,needs-special-reset;
			dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
			dma-names = "tx", "rx";
			status = "disabled";
			max-frequency = <192000000>;
			/* SDMA is not supported */
			sdhci-caps-mask = <0x0 0x400000>;
		};

		mmu0_dsp1: mmu@40d01000 {
Loading