Commit 8f97e221 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/pm: correct pcie spc cap setup 



Correct Polaris10 pcie spc cap setting.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ba4601fe

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

+2 −0
Original line number Diff line number Diff line
@@ -2865,6 +2865,8 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 
		data->pcie_gen_cap = adev->pm.pcie_gen_mask;

		if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)

			data->pcie_spc_cap = 20;

		else

			data->pcie_spc_cap = 16;

		data->pcie_lane_cap = adev->pm.pcie_mlw_mask;



		hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */