Commit 8e299e61 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-arm-dt-for-v5.10-tag1' of... 

Merge tag 'renesas-arm-dt-for-v5.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.10

  - Increase support for the RZ/G2H SoC on the HopeRun HiHope RZ/G2H
    board, and its display panel expansion board,
  - Increase support for the RZ/G1H SoC on the iWave RainboW SoM (G21M)
    and Qseven board (G21D),
  - SATA support for the HopeRun HiHope RZ/G2N board,
  - PCIe endpoint support for the RZ/G2M, RZ/G2E, and RZ/G2H SoCs,
  - Audio support for the R-Car M3-W+ SoC.
  - Minor fixes and improvements.

* tag 'renesas-arm-dt-for-v5.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (39 commits)
  arm64: dts: renesas: Add HiHope RZ/G2H board with idk-1110wr display
  arm64: dts: renesas: r8a774e1: Add cpuidle support for CA5x cores
  arm64: dts: renesas: r8a774e1: Add FDP1 device nodes
  ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller
  ARM: dts: r8a7742: Add IPMMU DT nodes
  arm64: dts: renesas: r8a77961: Enable Sound / Audio-DMAC
  arm64: dts: renesas: r8a774e1: Add PWM device nodes
  ARM: dts: r8a7742-iwg21m: Add SPI NOR support
  arm64: dts: renesas: r8a774e1-hihope-rzg2h: Enable HS400 mode
  ARM: dts: r8a7742-iwg21m: Add RTC support
  ARM: dts: r8a7742-iwg21m: Sort the nodes alphabetically
  ARM: dts: r8a7742: Add CAN support
  arm64: dts: renesas: r8a774c0: Add PCIe EP node
  arm64: dts: renesas: r8a774b1: Add PCIe EP nodes
  arm64: dts: renesas: r8a774a1: Add PCIe EP nodes
  ARM: dts: r8a7742: Add QSPI support
  arm64: dts: renesas: r8a774e1-hihope-rzg2h: Setup DU clocks
  arm64: dts: renesas: r8a774e1: Add LVDS device node
  arm64: dts: renesas: r8a774e1: Populate HDMI encoder node
  arm64: dts: renesas: r8a774e1: Populate DU device node
  ...

Link: https://lore.kernel.org/r/20200904114819.30254-3-geert+renesas@glider.be


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 20789171 e9f0fb53

arch/arm/boot/dts/r8a7742-iwg21d-q7.dts

+58 −0
Original line number Diff line number Diff line
@@ -131,6 +131,46 @@ sgtl5000: codec@a { 
	};

};



&cmt0 {

	status = "okay";

};



&hsusb {

	pinctrl-0 = <&usb0_pins>;

	pinctrl-names = "default";

	status = "okay";

};



&pci0 {

	pinctrl-0 = <&usb0_pins>;

	pinctrl-names = "default";

	/* Disable hsusb to enable USB2.0 host mode support on J2 */

	/* status = "okay"; */

};



&pci1 {

	pinctrl-0 = <&usb1_pins>;

	pinctrl-names = "default";

	status = "okay";

};



&pci2 {

	/* Disable xhci to enable USB2.0 host mode support on J23 bottom port */

	/* status = "okay"; */

};



&pcie_bus_clk {

	clock-frequency = <100000000>;

};



&pciec {

	/* SW2[6] determines which connector is activated

	 * ON = PCIe X4 (connector-J7)

	 * OFF = mini-PCIe (connector-J26)

	 */

	status = "okay";

};



&pfc {

	avb_pins: avb {

		groups = "avb_mdio", "avb_gmii";
@@ -168,6 +208,16 @@ sound_pins: sound { 
		groups = "ssi34_ctrl", "ssi3_data", "ssi4_data";

		function = "ssi";

	};



	usb0_pins: usb0 {

		groups = "usb0";

		function = "usb0";

	};



	usb1_pins: usb1 {

		groups = "usb1_pwen";

		function = "usb1";

	};

};



&rcar_sound {
@@ -222,3 +272,11 @@ &sdhi2 { 
&ssi4 {

	shared-pin;

};



&usbphy {

	status = "okay";

};



&xhci {

	status = "okay";

};

arch/arm/boot/dts/r8a7742-iwg21m.dtsi

+75 −4
Original line number Diff line number Diff line
@@ -35,10 +35,28 @@ &extal_clk { 
	clock-frequency = <20000000>;

};



&pfc {

	mmc1_pins: mmc1 {

		groups = "mmc1_data4", "mmc1_ctrl";

		function = "mmc1";

&gpio0 {

	/* GP0_18 set low to select QSPI. Doing so will disable VIN2 */

	qspi_en {

		gpio-hog;

		gpios = <18 GPIO_ACTIVE_HIGH>;

		output-low;

		line-name = "QSPI_EN";

	};

};



&i2c0 {

	pinctrl-0 = <&i2c0_pins>;

	pinctrl-names = "default";



	status = "okay";

	clock-frequency = <400000>;



	rtc@68 {

		compatible = "ti,bq32000";

		reg = <0x68>;

		interrupt-parent = <&gpio1>;

		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;

	};

};
@@ -51,3 +69,56 @@ &mmcif1 { 
	non-removable;

	status = "okay";

};



&pfc {

	i2c0_pins: i2c0 {

		groups = "i2c0";

		function = "i2c0";

	};



	mmc1_pins: mmc1 {

		groups = "mmc1_data4", "mmc1_ctrl";

		function = "mmc1";

	};



	qspi_pins: qspi {

		groups = "qspi_ctrl", "qspi_data2";

		function = "qspi";

	};

};



&qspi {

	pinctrl-0 = <&qspi_pins>;

	pinctrl-names = "default";



	status = "okay";



	flash: flash@0 {

		compatible = "sst,sst25vf016b", "jedec,spi-nor";

		reg = <0>;

		spi-max-frequency = <50000000>;

		m25p,fast-read;

		spi-cpol;

		spi-cpha;



		partitions {

			compatible = "fixed-partitions";

			#address-cells = <1>;

			#size-cells = <1>;



			partition@0 {

				label = "bootloader";

				reg = <0x00000000 0x000c0000>;

				read-only;

			};

			partition@c0000 {

				label = "env";

				reg = <0x000c0000 0x00002000>;

			};

			partition@c2000 {

				label = "user";

				reg = <0x000c2000 0x0013e000>;

			};

		};

	};

};

arch/arm/boot/dts/r8a7742.dtsi

+303 −0
Original line number Diff line number Diff line
@@ -36,6 +36,14 @@ audio_clk_c: audio_clk_c { 
		clock-frequency = <0>;

	};



	/* External CAN clock */

	can_clk: can {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		/* This value must be overridden by the board. */

		clock-frequency = <0>;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -188,6 +196,13 @@ extal_clk: extal { 
		clock-frequency = <0>;

	};



	/* External PCIe clock - can be overridden by the board */

	pcie_bus_clk: pcie_bus {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <0>;

	};



	pmu-0 {

		compatible = "arm,cortex-a15-pmu";

		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
@@ -328,6 +343,17 @@ pfc: pin-controller@e6060000 { 
			reg = <0 0xe6060000 0 0x250>;

		};



		tpu: pwm@e60f0000 {

			compatible = "renesas,tpu-r8a7742", "renesas,tpu";

			reg = <0 0xe60f0000 0 0x148>;

			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 304>;

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 304>;

			#pwm-cells = <3>;

			status = "disabled";

		};



		cpg: clock-controller@e6150000 {

			compatible = "renesas,r8a7742-cpg-mssr";

			reg = <0 0xe6150000 0 0x1000>;
@@ -386,6 +412,54 @@ thermal: thermal@e61f0000 { 
			#thermal-sensor-cells = <0>;

		};



		ipmmu_sy0: iommu@e6280000 {

			compatible = "renesas,ipmmu-r8a7742",

				     "renesas,ipmmu-vmsa";

			reg = <0 0xe6280000 0 0x1000>;

			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;

			#iommu-cells = <1>;

			status = "disabled";

		};



		ipmmu_sy1: iommu@e6290000 {

			compatible = "renesas,ipmmu-r8a7742",

				     "renesas,ipmmu-vmsa";

			reg = <0 0xe6290000 0 0x1000>;

			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;

			#iommu-cells = <1>;

			status = "disabled";

		};



		ipmmu_ds: iommu@e6740000 {

			compatible = "renesas,ipmmu-r8a7742",

				     "renesas,ipmmu-vmsa";

			reg = <0 0xe6740000 0 0x1000>;

			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;

			#iommu-cells = <1>;

			status = "disabled";

		};



		ipmmu_mp: iommu@ec680000 {

			compatible = "renesas,ipmmu-r8a7742",

				     "renesas,ipmmu-vmsa";

			reg = <0 0xec680000 0 0x1000>;

			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;

			#iommu-cells = <1>;

			status = "disabled";

		};



		ipmmu_mx: iommu@fe951000 {

			compatible = "renesas,ipmmu-r8a7742",

				     "renesas,ipmmu-vmsa";

			reg = <0 0xfe951000 0 0x1000>;

			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

			#iommu-cells = <1>;

			status = "disabled";

		};



		icram0: sram@e63a0000 {

			compatible = "mmio-sram";

			reg = <0 0xe63a0000 0 0x12000>;
@@ -683,6 +757,22 @@ avb: ethernet@e6800000 { 
			status = "disabled";

		};



		qspi: spi@e6b10000 {

			compatible = "renesas,qspi-r8a7742", "renesas,qspi";

			reg = <0 0xe6b10000 0 0x2c>;

			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 917>;

			dmas = <&dmac0 0x17>, <&dmac0 0x18>,

			       <&dmac1 0x17>, <&dmac1 0x18>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 917>;

			num-cs = <1>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		scifa0: serial@e6c40000 {

			compatible = "renesas,scifa-r8a7742",

				     "renesas,rcar-gen2-scifa", "renesas,scifa";
@@ -917,6 +1007,102 @@ msiof3: spi@e6c90000 { 
			status = "disabled";

		};



		can0: can@e6e80000 {

			compatible = "renesas,can-r8a7742",

				     "renesas,rcar-gen2-can";

			reg = <0 0xe6e80000 0 0x1000>;

			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 916>,

				 <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>;

			clock-names = "clkp1", "clkp2", "can_clk";

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 916>;

			status = "disabled";

		};



		can1: can@e6e88000 {

			compatible = "renesas,can-r8a7742",

				     "renesas,rcar-gen2-can";

			reg = <0 0xe6e88000 0 0x1000>;

			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 915>,

				 <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>;

			clock-names = "clkp1", "clkp2", "can_clk";

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 915>;

			status = "disabled";

		};



		pwm0: pwm@e6e30000 {

			compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";

			reg = <0 0xe6e30000 0 0x8>;

			clocks = <&cpg CPG_MOD 523>;

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 523>;

			#pwm-cells = <2>;

			status = "disabled";

		};



		pwm1: pwm@e6e31000 {

			compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";

			reg = <0 0xe6e31000 0 0x8>;

			clocks = <&cpg CPG_MOD 523>;

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 523>;

			#pwm-cells = <2>;

			status = "disabled";

		};



		pwm2: pwm@e6e32000 {

			compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";

			reg = <0 0xe6e32000 0 0x8>;

			clocks = <&cpg CPG_MOD 523>;

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 523>;

			#pwm-cells = <2>;

			status = "disabled";

		};



		pwm3: pwm@e6e33000 {

			compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";

			reg = <0 0xe6e33000 0 0x8>;

			clocks = <&cpg CPG_MOD 523>;

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 523>;

			#pwm-cells = <2>;

			status = "disabled";

		};



		pwm4: pwm@e6e34000 {

			compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";

			reg = <0 0xe6e34000 0 0x8>;

			clocks = <&cpg CPG_MOD 523>;

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 523>;

			#pwm-cells = <2>;

			status = "disabled";

		};



		pwm5: pwm@e6e35000 {

			compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";

			reg = <0 0xe6e35000 0 0x8>;

			clocks = <&cpg CPG_MOD 523>;

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 523>;

			#pwm-cells = <2>;

			status = "disabled";

		};



		pwm6: pwm@e6e36000 {

			compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";

			reg = <0 0xe6e36000 0 0x8>;

			clocks = <&cpg CPG_MOD 523>;

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 523>;

			#pwm-cells = <2>;

			status = "disabled";

		};



		rcar_sound: sound@ec500000 {

			/*

			 * #sound-dai-cells is required
@@ -1428,6 +1614,123 @@ gic: interrupt-controller@f1001000 { 
			resets = <&cpg 408>;

		};



		pciec: pcie@fe000000 {

			compatible = "renesas,pcie-r8a7742",

				     "renesas,pcie-rcar-gen2";

			reg = <0 0xfe000000 0 0x80000>;

			#address-cells = <3>;

			#size-cells = <2>;

			bus-range = <0x00 0xff>;

			device_type = "pci";

			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,

				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,

				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,

				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,

				     <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;

			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 319>;

			status = "disabled";

		};



		du: display@feb00000 {

			compatible = "renesas,du-r8a7742";

			reg = <0 0xfeb00000 0 0x70000>;

			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,

				 <&cpg CPG_MOD 722>;

			clock-names = "du.0", "du.1", "du.2";

			resets = <&cpg 724>;

			reset-names = "du.0";

			status = "disabled";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					du_out_rgb: endpoint {

					};

				};

				port@1 {

					reg = <1>;

					du_out_lvds0: endpoint {

						remote-endpoint = <&lvds0_in>;

					};

				};

				port@2 {

					reg = <2>;

					du_out_lvds1: endpoint {

						remote-endpoint = <&lvds1_in>;

					};

				};

			};

		};



		lvds0: lvds@feb90000 {

			compatible = "renesas,r8a7742-lvds";

			reg = <0 0xfeb90000 0 0x14>;

			clocks = <&cpg CPG_MOD 726>;

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 726>;

			status = "disabled";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					lvds0_in: endpoint {

						remote-endpoint = <&du_out_lvds0>;

					};

				};

				port@1 {

					reg = <1>;

					lvds0_out: endpoint {

					};

				};

			};

		};



		lvds1: lvds@feb94000 {

			compatible = "renesas,r8a7742-lvds";

			reg = <0 0xfeb94000 0 0x14>;

			clocks = <&cpg CPG_MOD 725>;

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 725>;

			status = "disabled";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					lvds1_in: endpoint {

						remote-endpoint = <&du_out_lvds1>;

					};

				};

				port@1 {

					reg = <1>;

					lvds1_out: endpoint {

					};

				};

			};

		};



		prr: chipid@ff000044 {

			compatible = "renesas,prr";

			reg = <0 0xff000044 0 4>;

arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts

+56 −56
Original line number Diff line number Diff line
@@ -53,42 +53,6 @@ audio_clock: audio_clock { 
		clock-frequency = <26000000>;

	};



	rsnd_sgtl5000: sound {

		compatible = "simple-audio-card";

		simple-audio-card,format = "i2s";

		simple-audio-card,bitclock-master = <&sndcodec>;

		simple-audio-card,frame-master = <&sndcodec>;



		sndcpu: simple-audio-card,cpu {

			sound-dai = <&rcar_sound>;

		};



		sndcodec: simple-audio-card,codec {

			sound-dai = <&sgtl5000>;

		};

	};



	vccq_sdhi0: regulator-vccq-sdhi0 {

		compatible = "regulator-gpio";



		regulator-name = "SDHI0 VccQ";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <3300000>;



		gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;

		gpios-states = <1>;

		states = <3300000 1>, <1800000 0>;

	};



	vccq_panel: regulator-vccq-panel {

		compatible = "regulator-fixed";

		regulator-name = "Panel VccQ";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;

		enable-active-high;

	};



	backlight_lcd: backlight {

		compatible = "pwm-backlight";

		pwms = <&tpu 3 5000000 PWM_POLARITY_INVERTED>;
@@ -107,19 +71,40 @@ lcd_in: endpoint { 
			};

		};

	};



	vccq_panel: regulator-vccq-panel {

		compatible = "regulator-fixed";

		regulator-name = "Panel VccQ";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;

		enable-active-high;

	};



&du {

	pinctrl-0 = <&du0_pins>;

	pinctrl-names = "default";

	vccq_sdhi0: regulator-vccq-sdhi0 {

		compatible = "regulator-gpio";



	status = "okay";

		regulator-name = "SDHI0 VccQ";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <3300000>;



	ports {

		port@0 {

			endpoint {

				remote-endpoint = <&lcd_in>;

		gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;

		gpios-states = <1>;

		states = <3300000 1>, <1800000 0>;

	};



	rsnd_sgtl5000: sound {

		compatible = "simple-audio-card";

		simple-audio-card,format = "i2s";

		simple-audio-card,bitclock-master = <&sndcodec>;

		simple-audio-card,frame-master = <&sndcodec>;



		sndcpu: simple-audio-card,cpu {

			sound-dai = <&rcar_sound>;

		};



		sndcodec: simple-audio-card,codec {

			sound-dai = <&sgtl5000>;

		};

	};

};
@@ -150,6 +135,21 @@ &can0 { 
	status = "okay";

};



&du {

	pinctrl-0 = <&du0_pins>;

	pinctrl-names = "default";



	status = "okay";



	ports {

		port@0 {

			endpoint {

				remote-endpoint = <&lcd_in>;

			};

		};

	};

};



&hscif1 {

	pinctrl-0 = <&hscif1_pins>;

	pinctrl-names = "default";
@@ -171,6 +171,15 @@ &i2c5 { 
	status = "okay";

	clock-frequency = <400000>;



	sgtl5000: codec@a {

		compatible = "fsl,sgtl5000";

		#sound-dai-cells = <0>;

		reg = <0x0a>;

		clocks = <&audio_clock>;

		VDDA-supply = <&reg_3p3v>;

		VDDIO-supply = <&reg_3p3v>;

	};



	stmpe811@44 {

		compatible = "st,stmpe811";

		reg = <0x44>;
@@ -179,7 +188,7 @@ stmpe811@44 { 


		/* 3.25 MHz ADC clock speed */

		st,adc-freq = <1>;

		/* ADC converstion time: 80 clocks */

		/* ADC conversion time: 80 clocks */

		st,sample-time = <4>;

		/* 12-bit ADC */

		st,mod-12b = <1>;
@@ -203,15 +212,6 @@ stmpe_touchscreen { 
			st,touch-det-delay = <5>;

		};

	};



	sgtl5000: codec@a {

		compatible = "fsl,sgtl5000";

		#sound-dai-cells = <0>;

		reg = <0x0a>;

		clocks = <&audio_clock>;

		VDDA-supply = <&reg_3p3v>;

		VDDIO-supply = <&reg_3p3v>;

	};

};



&pci1 {

arch/arm64/boot/dts/renesas/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-mipi-2.1.dtb 


dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb

dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb

dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb



dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb

dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb