Loading arch/arm/mach-mx1/clock.c +1 −1 Original line number Diff line number Diff line Loading @@ -626,7 +626,7 @@ int __init mx1_clocks_init(unsigned long fref) clk_enable(&hclk); clk_enable(&fclk); mxc_timer_init(&gpt_clk); mxc_timer_init(&gpt_clk, IO_ADDRESS(TIM1_BASE_ADDR), TIM1_INT); return 0; } arch/arm/mach-mx2/clock_imx21.c +1 −1 Original line number Diff line number Diff line Loading @@ -1004,6 +1004,6 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href) clk_enable(&uart_clk[0]); #endif mxc_timer_init(&gpt_clk[0]); mxc_timer_init(&gpt_clk[0], IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1); return 0; } arch/arm/mach-mx2/clock_imx27.c +1 −1 Original line number Diff line number Diff line Loading @@ -748,7 +748,7 @@ int __init mx27_clocks_init(unsigned long fref) clk_enable(&uart1_clk); #endif mxc_timer_init(&gpt1_clk); mxc_timer_init(&gpt1_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1); return 0; } Loading arch/arm/mach-mx3/clock-imx35.c +1 −1 Original line number Diff line number Diff line Loading @@ -456,7 +456,7 @@ int __init mx35_clocks_init() __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2); __raw_writel(0, CCM_BASE + CCM_CGR3); mxc_timer_init(&gpt_clk); mxc_timer_init(&ipg_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT); return 0; } Loading arch/arm/mach-mx3/clock.c +2 −1 Original line number Diff line number Diff line Loading @@ -29,6 +29,7 @@ #include <mach/clock.h> #include <mach/hardware.h> #include <mach/mx31.h> #include <mach/common.h> #include "crm_regs.h" Loading Loading @@ -609,7 +610,7 @@ int __init mx31_clocks_init(unsigned long fref) __raw_writel(reg, MXC_CCM_PMCR1); } mxc_timer_init(&ipg_clk); mxc_timer_init(&ipg_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT); return 0; } Loading Loading
arch/arm/mach-mx1/clock.c +1 −1 Original line number Diff line number Diff line Loading @@ -626,7 +626,7 @@ int __init mx1_clocks_init(unsigned long fref) clk_enable(&hclk); clk_enable(&fclk); mxc_timer_init(&gpt_clk); mxc_timer_init(&gpt_clk, IO_ADDRESS(TIM1_BASE_ADDR), TIM1_INT); return 0; }
arch/arm/mach-mx2/clock_imx21.c +1 −1 Original line number Diff line number Diff line Loading @@ -1004,6 +1004,6 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href) clk_enable(&uart_clk[0]); #endif mxc_timer_init(&gpt_clk[0]); mxc_timer_init(&gpt_clk[0], IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1); return 0; }
arch/arm/mach-mx2/clock_imx27.c +1 −1 Original line number Diff line number Diff line Loading @@ -748,7 +748,7 @@ int __init mx27_clocks_init(unsigned long fref) clk_enable(&uart1_clk); #endif mxc_timer_init(&gpt1_clk); mxc_timer_init(&gpt1_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1); return 0; } Loading
arch/arm/mach-mx3/clock-imx35.c +1 −1 Original line number Diff line number Diff line Loading @@ -456,7 +456,7 @@ int __init mx35_clocks_init() __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2); __raw_writel(0, CCM_BASE + CCM_CGR3); mxc_timer_init(&gpt_clk); mxc_timer_init(&ipg_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT); return 0; } Loading
arch/arm/mach-mx3/clock.c +2 −1 Original line number Diff line number Diff line Loading @@ -29,6 +29,7 @@ #include <mach/clock.h> #include <mach/hardware.h> #include <mach/mx31.h> #include <mach/common.h> #include "crm_regs.h" Loading Loading @@ -609,7 +610,7 @@ int __init mx31_clocks_init(unsigned long fref) __raw_writel(reg, MXC_CCM_PMCR1); } mxc_timer_init(&ipg_clk); mxc_timer_init(&ipg_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT); return 0; } Loading