Commit 8d7fb7a1 authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
Browse files

drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits 



Even though they are technically MMIO registers I put the bits with the sqind block
for organizational purposes.

Requested for UMR debugging.

Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 651a1465

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

+2 −1
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@@ -21,7 +21,8 @@ 
#ifndef _gc_10_1_0_OFFSET_HEADER

#define _gc_10_1_0_OFFSET_HEADER

















#define mmSQ_DEBUG_STS_GLOBAL                                                                          0x2309









#define mmSQ_DEBUG_STS_GLOBAL2                                                                         0x2310

















// addressBlock: gc_sdma0_sdma0dec









// base address: 0x4980

























drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h



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@@ -42546,6 +42546,22 @@























// addressBlock: sqind









//SQ_DEBUG_STS_GLOBAL









#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL









#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000









#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L









#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008









#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE_MASK 0xff0000L









#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE__SHIFT 0x00000010









#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L









#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000









#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L









#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001









#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0_MASK 0x0000fff0L









#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0__SHIFT 0x00000004









#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1_MASK 0x0fff0000L









#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1__SHIFT 0x00000010

















//SQ_DEBUG_STS_LOCAL









#define SQ_DEBUG_STS_LOCAL__BUSY_MASK                                                                         0x00000001L









#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT                                                                       0x00000000

























drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h



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#ifndef _gc_10_3_0_OFFSET_HEADER









#define _gc_10_3_0_OFFSET_HEADER

























#define mmSQ_DEBUG_STS_GLOBAL                                                                          0x2309









#define mmSQ_DEBUG_STS_GLOBAL2                                                                         0x2310

















// addressBlock: gc_sdma0_sdma0dec









// base address: 0x4980

























drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h



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@@ -46269,6 +46269,22 @@























// addressBlock: sqind









//SQ_DEBUG_STS_GLOBAL









#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL









#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000









#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L









#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008









#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE_MASK 0xff0000L









#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE__SHIFT 0x00000010









#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L









#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000









#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L









#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001









#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0_MASK 0x0000fff0L









#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0__SHIFT 0x00000004









#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1_MASK 0x0fff0000L









#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1__SHIFT 0x00000010

















//SQ_DEBUG_STS_LOCAL









#define SQ_DEBUG_STS_LOCAL__BUSY_MASK                                                                         0x00000001L









#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT                                                                       0x00000000

























drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h



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#ifndef _gc_9_0_OFFSET_HEADER









#define _gc_9_0_OFFSET_HEADER

























#define mmSQ_DEBUG_STS_GLOBAL                                                                          0x2309









#define mmSQ_DEBUG_STS_GLOBAL2                                                                         0x2310









#define mmSQ_DEBUG_STS_GLOBAL3                                                                         0x2311

















// addressBlock: gc_grbmdec









// base address: 0x8000