Unverified Commit 8d4f9145 authored Oct 20, 2023 by Pierre Gondois Committed by Arnd Bergmann Oct 23, 2023

arm64: dts: Update cache properties for socionext



The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20221107155825.1644604-21-pierre.gondois@arm.com


Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231020195022.4183862-2-robh@kernel.org


Signed-off-by: Arnd Bergmann <arnd@arndb.de>

parent 23b336e9

arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -52,6 +52,7 @@ cpu1: cpu@1 {

		l2: l2-cache {
		compatible = "cache";
		cache-level = <2>;
		};
		};

arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -86,10 +86,12 @@ cpu3: cpu@101 {

		a72_l2: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		};

		a53_l2: l2-cache1 {
		compatible = "cache";
		cache-level = <2>;
		};
		};

arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -83,6 +83,7 @@ cpu3: cpu@3 {

		l2: l2-cache {
		compatible = "cache";
		cache-level = <2>;
		};
		};