Commit 8cf3dccb authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amdgpu: Enable CP idle interrupts 



v1: The interrupts need to be enabled to move to DS clocks.
v2: Don't enable GFX IDLE interrupts if there are no GFX rings.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8a6b6b66

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+3 −5
Original line number Diff line number Diff line
@@ -2669,16 +2669,14 @@ static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 
{

	u32 tmp;



	/* don't toggle interrupts that are only applicable

	 * to me0 pipe0 on AISCs that have me0 removed */

	if (!adev->gfx.num_gfx_rings)

		return;

	/* These interrupts should be enabled to drive DS clock */



	tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);



	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);

	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);

	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);

	if(adev->gfx.num_gfx_rings)

		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);



	WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);