Commit 8c563f55 authored by Zhen Lei's avatar Zhen Lei Committed by Wei Xu
Browse files

arm64: dts: hisilicon: write the values of property-units into a uint32 array 



Use <> to separate the values of property-units will be treated as
multiple arrays. The errors similar to the following will be reported by
property-units.yaml.

ufs@ff3c0000: freq-table-hz: [[0, 0], [0, 0]] is too long

Signed-off-by: default avatarZhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: default avatarWei Xu <xuwei5@hisilicon.com>
parent 24402ce1

arch/arm64/boot/dts/hisilicon/hi3660.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -1045,7 +1045,8 @@ ufs: ufs@ff3b0000 { 
			clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,

				<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;

			clock-names = "ref_clk", "phy_clk";

			freq-table-hz = <0 0>, <0 0>;

			freq-table-hz = <0 0

					 0 0>;

			/* offset: 0x84; bit: 12 */

			resets = <&crg_rst 0x84 12>;

			reset-names = "rst";

arch/arm64/boot/dts/hisilicon/hi3670.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -667,7 +667,8 @@ ufs: ufs@ff3c0000 { 
			clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,

				<&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;

			clock-names = "ref_clk", "phy_clk";

			freq-table-hz = <0 0>, <0 0>;

			freq-table-hz = <0 0

					 0 0>;

			/* offset: 0x84; bit: 12 */

			resets = <&crg_rst 0x84 12>;

			reset-names = "rst";

arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi

+4 −5
Original line number Diff line number Diff line
@@ -91,11 +91,10 @@ crg: clock-reset-controller@8a22000 { 
			gmacphyrst: reset-controller {

				compatible = "ti,syscon-reset";

				#reset-cells = <1>;

				ti,reset-bits =

					<0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |

					 DEASSERT_SET|STATUS_NONE)>,

					<0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |

					 DEASSERT_SET|STATUS_NONE)>;

				ti,reset-bits = <

					0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)

					0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)

				>;

			};

		};