Commit 8be6e49a authored by Marcel Ziswiler's avatar Marcel Ziswiler Committed by Thierry Reding
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ARM: tegra: apalis-tk1: enable emmc ddr52 mode 



Add mmc-ddr-1_8v property enabling eMMC DDR52 mode.

root@apalis-tk1-mainline:~# cat /sys/kernel/debug/mmc2/ios
clock:          52000000 Hz
actual clock:   52000000 Hz
vdd:            21 (3.3 ~ 3.4 V)
bus mode:       2 (push-pull)
chip select:    0 (don't care)
power mode:     2 (on)
bus width:      3 (8 bits)
timing spec:    8 (mmc DDR52)
signal voltage: 1 (1.80 V)
driver type:    0 (driver type B)
root@apalis-tk1-mainline:~# hdparm -t /dev/mmcblk2

/dev/mmcblk2:
 Timing buffered disk reads: 256 MB in  3.02 seconds =  84.83 MB/sec

Signed-off-by: default avatarMarcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent fca051b0

arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -1919,6 +1919,7 @@ sdhci@700b0600 { 
		non-removable;

		vmmc-supply = <&reg_module_3v3>; /* VCC */

		vqmmc-supply = <&reg_1v8_vddio>; /* VCCQ */

		mmc-ddr-1_8v;

	};



	/* CPU DFLL clock */

arch/arm/boot/dts/tegra124-apalis.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -1948,6 +1948,7 @@ sdhci@700b0600 { 
		non-removable;

		vmmc-supply = <&reg_module_3v3>; /* VCC */

		vqmmc-supply = <&reg_1v8_vddio>; /* VCCQ */

		mmc-ddr-1_8v;

	};



	/* CPU DFLL clock */