Unverified Commit 89c500b1 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'reset-for-v5.19' of git://git.pengutronix.de/pza/linux into arm/drivers 

Reset controller updates for v5.19

Add Meson-S4 SoC reset controller support to reset-meson, AST2600 LPC
reset controller support to reset-simple, and R9A07G054 USBPHY reset
controller support to reset-rzg2l-usbphy-ctrl. Add ACPI _RST support to
device_reset(), simplify the uniphier-glue reset driver using bulk API
and devres and clean up its dt-bindings docs. Convert most dt-bindings
docs from txt to yaml.

* tag 'reset-for-v5.19' of git://git.pengutronix.de/pza/linux:
  dt-bindings: reset: st,sti-powerdown: Convert to yaml
  dt-bindings: reset: st,sti-picophyreset: Convert to yaml
  dt-bindings: reset: socfpga: Convert to yaml
  dt-bindings: reset: snps,axs10x-reset: Convert to yaml
  dt-bindings: reset: nuvoton,npcm-reset: Convert to yaml
  dt-bindings: reset: lantiq,reset: Convert to yaml
  dt-bindings: reset: bitmain,bm1880-reset: Convert to yaml
  dt-bindings: reset: berlin: Convert to yaml
  dt-bindings: reset: ath79: Convert to yaml
  dt-bindings: reset: amlogic,meson-axg-audio-arb: Convert to yaml
  dt-bindings: reset: uniphier-glue: Clean up clocks, resets, and their names using compatible string
  reset: Kconfig: Make RESET_RZG2L_USBPHY_CTRL depend on ARCH_RZG2L
  reset: ACPI reset support
  reset: simple: Add AST2600 compatible
  reset: reset-meson: add support for the Meson-S4 SoC Reset Controller
  dt-bindings: reset: add bindings for the Meson-S4 SoC Reset Controller
  dt-bindings: reset: Add compatible for Meson-S4 Reset Controller
  reset: uniphier-glue: Use devm_add_action_or_reset()
  reset: uniphier-glue: Use reset_control_bulk API

Link: https://lore.kernel.org/r/20220503160057.46625-1-p.zabel@pengutronix.de


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 4d7b3fd9 2ca065dc

Documentation/devicetree/bindings/reset/altr,rst-mgr.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/reset/altr,rst-mgr.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Altera SOCFPGA Reset Manager



maintainers:

  - Dinh Nguyen <dinguyen@altera.com>



properties:

  compatible:

    oneOf:

      - description: Cyclone5/Arria5/Arria10

        const: altr,rst-mgr

      - description: Stratix10 ARM64 SoC

        items:

          - const: altr,stratix10-rst-mgr

          - const: altr,rst-mgr



  reg:

    maxItems: 1



  altr,modrst-offset:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: Offset of the first modrst register



  '#reset-cells':

    const: 1



required:

  - compatible

  - reg

  - altr,modrst-offset

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    rstmgr@ffd05000 {

        compatible = "altr,rst-mgr";

        reg = <0xffd05000 0x1000>;

        altr,modrst-offset = <0x10>;

        #reset-cells = <1>;

    };

Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt

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* Amlogic audio memory arbiter controller



The Amlogic Audio ARB is a simple device which enables or

disables the access of Audio FIFOs to DDR on AXG based SoC.



Required properties:

- compatible: 'amlogic,meson-axg-audio-arb' or

	      'amlogic,meson-sm1-audio-arb'

- reg: physical base address of the controller and length of memory

       mapped region.

- clocks: phandle to the fifo peripheral clock provided by the audio

	  clock controller.

- #reset-cells: must be 1.



Example on the A113 SoC:



arb: reset-controller@280 {

	compatible = "amlogic,meson-axg-audio-arb";

	reg = <0x0 0x280 0x0 0x4>;

	#reset-cells = <1>;

	clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;

};

Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright 2019 BayLibre, SAS

%YAML 1.2

---

$id: "http://devicetree.org/schemas/reset/amlogic,meson-axg-audio-arb.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Amlogic audio memory arbiter controller



maintainers:

  - Jerome Brunet <jbrunet@baylibre.com>



description: The Amlogic Audio ARB is a simple device which enables or disables

  the access of Audio FIFOs to DDR on AXG based SoC.



properties:

  compatible:

    enum:

      - amlogic,meson-axg-audio-arb

      - amlogic,meson-sm1-audio-arb



  reg:

    maxItems: 1



  clocks:

    maxItems: 1

    description: |

      phandle to the fifo peripheral clock provided by the audio clock

      controller.



  "#reset-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - "#reset-cells"



additionalProperties: false



examples:

  - |

    // on the A113 SoC:

    #include <dt-bindings/clock/axg-audio-clkc.h>

    bus {

        #address-cells = <2>;

        #size-cells = <2>;



        arb: reset-controller@280 {

            compatible = "amlogic,meson-axg-audio-arb";

            reg = <0x0 0x280 0x0 0x4>;

            #reset-cells = <1>;

            clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;

        };

    };

Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml

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@@ -17,6 +17,7 @@ properties: 
      - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs

      - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs

      - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs

      - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs



  reg:

    maxItems: 1

Documentation/devicetree/bindings/reset/ath79-reset.txt

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Binding for Qualcomm Atheros AR7xxx/AR9XXX reset controller



Please also refer to reset.txt in this directory for common reset

controller binding usage.



Required Properties:

- compatible: has to be "qca,<soctype>-reset", "qca,ar7100-reset"

              as fallback

- reg: Base address and size of the controllers memory area

- #reset-cells : Specifies the number of cells needed to encode reset

                 line, should be 1



Example:



	reset-controller@1806001c {

		compatible = "qca,ar9132-reset", "qca,ar7100-reset";

		reg = <0x1806001c 0x4>;



		#reset-cells = <1>;

	};