Commit 85f4bc0c authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Add SubVP required code 



This commit enables the SubVP feature. To achieve that, we need to:

- Don't force p-state disallow on SubVP (can't block dummy p-state)
- Send calculated watermark to DMCUB for SubVP
- Adjust CAB mode message to PMFW
- Add a proper locking sequence for SubVP
- Various fixes to SubVP static analysis and determining SubVP config
- Currently SubVP not supported with pipe split so merge all pipes
  before setting up SubVp

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: default avatarAlan Liu <HaoPing.Liu@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e72f03f4

drivers/gpu/drm/amd/display/dc/Makefile

+26 −1
Original line number Diff line number Diff line
@@ -21,7 +21,31 @@ 
#

#

# Makefile for Display Core (dc) component.

#



ifdef CONFIG_X86

dmub_ccflags := -mhard-float -msse

endif



ifdef CONFIG_PPC64

dmub_ccflags := -mhard-float -maltivec

endif



ifdef CONFIG_CC_IS_GCC

ifeq ($(call cc-ifversion, -lt, 0701, y), y)

IS_OLD_GCC = 1

endif

endif



ifdef CONFIG_X86

ifdef IS_OLD_GCC

# Stack alignment mismatch, proceed with caution.

# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3

# (8B stack alignment).

dmub_ccflags += -mpreferred-stack-boundary=4

else

dmub_ccflags += -msse2

endif

endif



DC_LIBS = basics bios dml clk_mgr dce gpio irq link virtual
@@ -75,6 +99,7 @@ AMD_DISPLAY_FILES += $(AMD_DISPLAY_CORE) 
AMD_DISPLAY_FILES += $(AMD_DM_REG_UPDATE)



DC_DMUB += dc_dmub_srv.o

CFLAGS_$(AMDDALPATH)/dc/dc_dmub_srv.o := $(dmub_ccflags)

DC_EDID += dc_edid_parser.o

AMD_DISPLAY_DMUB = $(addprefix $(AMDDALPATH)/dc/,$(DC_DMUB))

AMD_DISPLAY_EDID = $(addprefix $(AMDDALPATH)/dc/,$(DC_EDID))

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

+6 −0
Original line number Diff line number Diff line
@@ -58,6 +58,12 @@ int clk_mgr_helper_get_active_display_cnt( 
	for (i = 0; i < context->stream_count; i++) {

		const struct dc_stream_state *stream = context->streams[i];



		/* Don't count SubVP phantom pipes as part of active

		 * display count

		 */

		if (stream->mall_stream_config.type == SUBVP_PHANTOM)

			continue;



		/*

		 * Only notify active stream or virtual stream.

		 * Need to notify virtual stream to work around

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

+3 −2
Original line number Diff line number Diff line
@@ -100,9 +100,10 @@ void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool e 


void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways)

{

	smu_print("Numways for SubVP : %d\n", num_ways);

	uint32_t param = (num_ways << 1) | (num_ways > 0);



	dcn32_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetCabForUclkPstate, num_ways, NULL);

	dcn32_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetCabForUclkPstate, param, NULL);

	smu_print("Numways for SubVP : %d\n", num_ways);

}



void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/core/dc.c

+64 −1
Original line number Diff line number Diff line
@@ -1905,7 +1905,8 @@ static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context) 
	for (i = 0; i < MAX_PIPES; i++) {

		pipe = &context->res_ctx.pipe_ctx[i];



		if (!pipe->plane_state)

		// Don't check flip pending on phantom pipes

		if (!pipe->plane_state || (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM))

			continue;



		/* Must set to false to start with, due to OR in update function */
@@ -2917,6 +2918,13 @@ static void commit_planes_for_stream(struct dc *dc, 
	int i, j;

	struct pipe_ctx *top_pipe_to_program = NULL;

	bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST);

	bool subvp_prev_use = false;



	// Once we apply the new subvp context to hardware it won't be in the

	// dc->current_state anymore, so we have to cache it before we apply

	// the new SubVP context

	subvp_prev_use = false;





	dc_z10_restore(dc);
@@ -2955,6 +2963,15 @@ static void commit_planes_for_stream(struct dc *dc, 
		}

	}



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];



		// Check old context for SubVP

		subvp_prev_use |= (old_pipe->stream && old_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM);

		if (subvp_prev_use)

			break;

	}



	if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {

		struct pipe_ctx *mpcc_pipe;

		struct pipe_ctx *odm_pipe;
@@ -2984,8 +3001,13 @@ static void commit_planes_for_stream(struct dc *dc, 
		}



	if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {

		if (dc->hwss.subvp_pipe_control_lock)

				dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, NULL, subvp_prev_use);

		dc->hwss.interdependent_update_lock(dc, context, true);



	} else {

		if (dc->hwss.subvp_pipe_control_lock)

			dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);

		/* Lock the top pipe while updating plane addrs, since freesync requires

		 *  plane addr update event triggers to be synchronized.

		 *  top_pipe_to_program is expected to never be NULL
@@ -2993,8 +3015,40 @@ static void commit_planes_for_stream(struct dc *dc, 
		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);

	}



	if (update_type != UPDATE_TYPE_FAST) {

		for (i = 0; i < dc->res_pool->pipe_count; i++) {

			struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];



			if ((new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) ||

					subvp_prev_use) {

				// If old context or new context has phantom pipes, apply

				// the phantom timings now. We can't change the phantom

				// pipe configuration safely without driver acquiring

				// the DMCUB lock first.

				dc->hwss.apply_ctx_to_hw(dc, context);

				break;

			}

		}

	}



	dc_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context);



	if (update_type != UPDATE_TYPE_FAST) {

		for (i = 0; i < dc->res_pool->pipe_count; i++) {

			struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];



			if ((new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) ||

					subvp_prev_use) {

				// If old context or new context has phantom pipes, apply

				// the phantom timings now. We can't change the phantom

				// pipe configuration safely without driver acquiring

				// the DMCUB lock first.

				dc->hwss.apply_ctx_to_hw(dc, context);

				break;

			}

		}

	}



	// Stream updates

	if (stream_update)

		commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
@@ -3009,11 +3063,20 @@ static void commit_planes_for_stream(struct dc *dc, 
		if (dc->hwss.program_front_end_for_ctx)

			dc->hwss.program_front_end_for_ctx(dc, context);



		if (update_type != UPDATE_TYPE_FAST)

			if (dc->hwss.commit_subvp_config)

				dc->hwss.commit_subvp_config(dc, context);



		if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {

			dc->hwss.interdependent_update_lock(dc, context, false);

			if (dc->hwss.subvp_pipe_control_lock)

				dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use);

		} else {

			dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);

			if (dc->hwss.subvp_pipe_control_lock)

				dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use);

		}



		dc->hwss.post_unlock_program_front_end(dc, context);

		return;

	}

drivers/gpu/drm/amd/display/dc/dc.h

+0 −2
Original line number Diff line number Diff line
@@ -207,7 +207,6 @@ struct dc_caps { 
	bool vbios_lttpr_aware;

	bool vbios_lttpr_enable;

	uint32_t max_otg_num;

#ifdef CONFIG_DRM_AMD_DC_DCN

	uint32_t max_cab_allocation_bytes;

	uint32_t cache_line_size;

	uint32_t cache_num_ways;
@@ -215,7 +214,6 @@ struct dc_caps { 
	uint16_t subvp_prefetch_end_to_mall_start_us;

	uint16_t subvp_pstate_allow_width_us;

	uint16_t subvp_vertical_int_margin_us;

#endif

	bool seamless_odm;

};