Loading MAINTAINERS +1 −0 Original line number Diff line number Diff line Loading @@ -2537,6 +2537,7 @@ W: http://www.armlinux.org.uk/ ARM/QUALCOMM SUPPORT M: Andy Gross <agross@kernel.org> M: Bjorn Andersson <bjorn.andersson@linaro.org> R: Konrad Dybcio <konrad.dybcio@somainline.org> L: linux-arm-msm@vger.kernel.org S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git Loading arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -74,7 +74,7 @@ pm8994_regulators: pm8994-regulators { vdd_l17_29-supply = <&vph_pwr>; vdd_l20_21-supply = <&vph_pwr>; vdd_l25-supply = <&pm8994_s5>; vdd_lvs1_2 = <&pm8994_s4>; vdd_lvs1_2-supply = <&pm8994_s4>; /* S1, S2, S6 and S12 are managed by RPMPD */ Loading arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +1 −1 Original line number Diff line number Diff line Loading @@ -169,7 +169,7 @@ pm8994-regulators { vdd_l17_29-supply = <&vph_pwr>; vdd_l20_21-supply = <&vph_pwr>; vdd_l25-supply = <&pm8994_s5>; vdd_lvs1_2 = <&pm8994_s4>; vdd_lvs1_2-supply = <&pm8994_s4>; /* S1, S2, S6 and S12 are managed by RPMPD */ Loading arch/arm64/boot/dts/qcom/msm8994.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -100,7 +100,7 @@ CPU5: cpu@101 { CPU6: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x101>; reg = <0x0 0x102>; enable-method = "psci"; next-level-cache = <&L2_1>; }; Loading @@ -108,7 +108,7 @@ CPU6: cpu@102 { CPU7: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x101>; reg = <0x0 0x103>; enable-method = "psci"; next-level-cache = <&L2_1>; }; Loading arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -5,7 +5,7 @@ * Copyright 2021 Google LLC. */ #include "sc7180-trogdor.dtsi" /* This file must be included after sc7180-trogdor.dtsi */ / { /* BOARD-SPECIFIC TOP LEVEL NODES */ Loading Loading
MAINTAINERS +1 −0 Original line number Diff line number Diff line Loading @@ -2537,6 +2537,7 @@ W: http://www.armlinux.org.uk/ ARM/QUALCOMM SUPPORT M: Andy Gross <agross@kernel.org> M: Bjorn Andersson <bjorn.andersson@linaro.org> R: Konrad Dybcio <konrad.dybcio@somainline.org> L: linux-arm-msm@vger.kernel.org S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git Loading
arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -74,7 +74,7 @@ pm8994_regulators: pm8994-regulators { vdd_l17_29-supply = <&vph_pwr>; vdd_l20_21-supply = <&vph_pwr>; vdd_l25-supply = <&pm8994_s5>; vdd_lvs1_2 = <&pm8994_s4>; vdd_lvs1_2-supply = <&pm8994_s4>; /* S1, S2, S6 and S12 are managed by RPMPD */ Loading
arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +1 −1 Original line number Diff line number Diff line Loading @@ -169,7 +169,7 @@ pm8994-regulators { vdd_l17_29-supply = <&vph_pwr>; vdd_l20_21-supply = <&vph_pwr>; vdd_l25-supply = <&pm8994_s5>; vdd_lvs1_2 = <&pm8994_s4>; vdd_lvs1_2-supply = <&pm8994_s4>; /* S1, S2, S6 and S12 are managed by RPMPD */ Loading
arch/arm64/boot/dts/qcom/msm8994.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -100,7 +100,7 @@ CPU5: cpu@101 { CPU6: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x101>; reg = <0x0 0x102>; enable-method = "psci"; next-level-cache = <&L2_1>; }; Loading @@ -108,7 +108,7 @@ CPU6: cpu@102 { CPU7: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0 0x101>; reg = <0x0 0x103>; enable-method = "psci"; next-level-cache = <&L2_1>; }; Loading
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -5,7 +5,7 @@ * Copyright 2021 Google LLC. */ #include "sc7180-trogdor.dtsi" /* This file must be included after sc7180-trogdor.dtsi */ / { /* BOARD-SPECIFIC TOP LEVEL NODES */ Loading