Commit 810085dd authored by Eric Huang's avatar Eric Huang Committed by Alex Deucher
Browse files

drm/amdgpu: Don't flush/invalidate HDP for APUs and A+A 



Integrate two generic functions to determine if HDP
flush is needed for all Asics.

Signed-off-by: default avatarEric Huang <jinhuieric.huang@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9fd4781b

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+5 −0
Original line number Diff line number Diff line
@@ -1285,6 +1285,11 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 
int amdgpu_device_baco_enter(struct drm_device *dev);

int amdgpu_device_baco_exit(struct drm_device *dev);



void amdgpu_device_flush_hdp(struct amdgpu_device *adev,

		struct amdgpu_ring *ring);

void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,

		struct amdgpu_ring *ring);



/* atpx handler */

#if defined(CONFIG_VGA_SWITCHEROO)

void amdgpu_register_atpx_handler(void);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+29 −2
Original line number Diff line number Diff line
@@ -313,9 +313,9 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 
		if (write) {

			memcpy_toio(addr, buf, count);

			mb();

			amdgpu_asic_flush_hdp(adev, NULL);

			amdgpu_device_flush_hdp(adev, NULL);

		} else {

			amdgpu_asic_invalidate_hdp(adev, NULL);

			amdgpu_device_invalidate_hdp(adev, NULL);

			mb();

			memcpy_fromio(buf, addr, count);

		}
@@ -5475,4 +5475,31 @@ bool amdgpu_device_load_pci_state(struct pci_dev *pdev) 
	return true;

}



void amdgpu_device_flush_hdp(struct amdgpu_device *adev,

		struct amdgpu_ring *ring)

{

#ifdef CONFIG_X86_64

	if (adev->flags & AMD_IS_APU)

		return;

#endif

	if (adev->gmc.xgmi.connected_to_cpu)

		return;



	if (ring && ring->funcs->emit_hdp_flush)

		amdgpu_ring_emit_hdp_flush(ring);

	else

		amdgpu_asic_flush_hdp(adev, ring);

}



void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,

		struct amdgpu_ring *ring)

{

#ifdef CONFIG_X86_64

	if (adev->flags & AMD_IS_APU)

		return;

#endif

	if (adev->gmc.xgmi.connected_to_cpu)

		return;



	amdgpu_asic_invalidate_hdp(adev, ring);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c

+2 −2
Original line number Diff line number Diff line
@@ -250,7 +250,7 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 
		}

	}

	mb();

	amdgpu_asic_flush_hdp(adev, NULL);

	amdgpu_device_flush_hdp(adev, NULL);

	for (i = 0; i < adev->num_vmhubs; i++)

		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
@@ -337,7 +337,7 @@ void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev) 
	int i;



	mb();

	amdgpu_asic_flush_hdp(adev, NULL);

	amdgpu_device_flush_hdp(adev, NULL);

	for (i = 0; i < adev->num_vmhubs; i++)

		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

+2 −13
Original line number Diff line number Diff line
@@ -214,15 +214,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
	if (job && ring->funcs->init_cond_exec)

		patch_offset = amdgpu_ring_init_cond_exec(ring);



#ifdef CONFIG_X86_64

	if (!(adev->flags & AMD_IS_APU))

#endif

	{

		if (ring->funcs->emit_hdp_flush)

			amdgpu_ring_emit_hdp_flush(ring);

		else

			amdgpu_asic_flush_hdp(adev, ring);

	}

	amdgpu_device_flush_hdp(adev, ring);



	if (need_ctx_switch)

		status |= AMDGPU_HAVE_CTX_SWITCH;
@@ -259,10 +251,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
	if (job && ring->funcs->emit_frame_cntl)

		amdgpu_ring_emit_frame_cntl(ring, false, secure);



#ifdef CONFIG_X86_64

	if (!(adev->flags & AMD_IS_APU))

#endif

		amdgpu_asic_invalidate_hdp(adev, ring);

	amdgpu_device_invalidate_hdp(adev, ring);



	if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE)

		fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY;

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+3 −3
Original line number Diff line number Diff line
@@ -282,7 +282,7 @@ psp_cmd_submit_buf(struct psp_context *psp, 
		goto exit;

	}



	amdgpu_asic_invalidate_hdp(psp->adev, NULL);

	amdgpu_device_invalidate_hdp(psp->adev, NULL);

	while (*((unsigned int *)psp->fence_buf) != index) {

		if (--timeout == 0)

			break;
@@ -295,7 +295,7 @@ psp_cmd_submit_buf(struct psp_context *psp, 
		if (ras_intr)

			break;

		usleep_range(10, 100);

		amdgpu_asic_invalidate_hdp(psp->adev, NULL);

		amdgpu_device_invalidate_hdp(psp->adev, NULL);

	}



	/* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
@@ -2696,7 +2696,7 @@ int psp_ring_cmd_submit(struct psp_context *psp, 
	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);

	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);

	write_frame->fence_value = index;

	amdgpu_asic_flush_hdp(adev, NULL);

	amdgpu_device_flush_hdp(adev, NULL);



	/* Update the write Pointer in DWORDs */

	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;