Commit 7cee6a68 authored by Jonathan Kim's avatar Jonathan Kim Committed by Alex Deucher
Browse files

drm/amdgpu: add configurable grace period for unmap queues 



The HWS schedule allows a grace period for wave completion prior to
preemption for better performance by avoiding CWSR on waves that can
potentially complete quickly. The debugger, on the other hand, will
want to inspect wave status immediately after it actively triggers
preemption (a suspend function to be provided).

To minimize latency between preemption and debugger wave inspection, allow
immediate preemption by setting the grace period to 0.

Note that setting the preepmtion grace period to 0 will result in an
infinite grace period being set due to a CP FW bug so set it to 1 for now.

Signed-off-by: default avatarJonathan Kim <jonathan.kim@amd.com>
Reviewed-by: default avatarFelix Kuehling <felix.kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 33f3437a

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

+2 −0
Original line number Diff line number Diff line
@@ -82,5 +82,7 @@ const struct kfd2kgd_calls aldebaran_kfd2kgd = { 
	.get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy,

	.enable_debug_trap = kgd_aldebaran_enable_debug_trap,

	.disable_debug_trap = kgd_aldebaran_disable_debug_trap,

	.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,

	.build_grace_period_packet_info = kgd_gfx_v9_build_grace_period_packet_info,

	.program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings,

};

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

+2 −0
Original line number Diff line number Diff line
@@ -410,6 +410,8 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = { 
				kgd_gfx_v9_set_vm_context_page_table_base,

	.enable_debug_trap = kgd_arcturus_enable_debug_trap,

	.disable_debug_trap = kgd_arcturus_disable_debug_trap,

	.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,

	.build_grace_period_packet_info = kgd_gfx_v9_build_grace_period_packet_info,

	.get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy,

	.program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings

};

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

+43 −0
Original line number Diff line number Diff line
@@ -803,6 +803,47 @@ uint32_t kgd_gfx_v10_disable_debug_trap(struct amdgpu_device *adev, 
	return 0;

}



/* kgd_gfx_v10_get_iq_wait_times: Returns the mmCP_IQ_WAIT_TIME1/2 values

 * The values read are:

 *     ib_offload_wait_time     -- Wait Count for Indirect Buffer Offloads.

 *     atomic_offload_wait_time -- Wait Count for L2 and GDS Atomics Offloads.

 *     wrm_offload_wait_time    -- Wait Count for WAIT_REG_MEM Offloads.

 *     gws_wait_time            -- Wait Count for Global Wave Syncs.

 *     que_sleep_wait_time      -- Wait Count for Dequeue Retry.

 *     sch_wave_wait_time       -- Wait Count for Scheduling Wave Message.

 *     sem_rearm_wait_time      -- Wait Count for Semaphore re-arm.

 *     deq_retry_wait_time      -- Wait Count for Global Wave Syncs.

 */

void kgd_gfx_v10_get_iq_wait_times(struct amdgpu_device *adev,

					uint32_t *wait_times)



{

	*wait_times = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2));

}



void kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev,

						uint32_t wait_times,

						uint32_t grace_period,

						uint32_t *reg_offset,

						uint32_t *reg_data)

{

	*reg_data = wait_times;



	/*

	 * The CP cannont handle a 0 grace period input and will result in

	 * an infinite grace period being set so set to 1 to prevent this.

	 */

	if (grace_period == 0)

		grace_period = 1;



	*reg_data = REG_SET_FIELD(*reg_data,

			CP_IQ_WAIT_TIME2,

			SCH_WAVE,

			grace_period);



	*reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2);

}



static void program_trap_handler_settings(struct amdgpu_device *adev,

		uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr,

		uint32_t inst)
@@ -848,5 +889,7 @@ const struct kfd2kgd_calls gfx_v10_kfd2kgd = { 
	.set_vm_context_page_table_base = set_vm_context_page_table_base,

	.enable_debug_trap = kgd_gfx_v10_enable_debug_trap,

	.disable_debug_trap = kgd_gfx_v10_disable_debug_trap,

	.get_iq_wait_times = kgd_gfx_v10_get_iq_wait_times,

	.build_grace_period_packet_info = kgd_gfx_v10_build_grace_period_packet_info,

	.program_trap_handler_settings = program_trap_handler_settings,

};

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

+6 −0
Original line number Diff line number Diff line
@@ -26,3 +26,9 @@ uint32_t kgd_gfx_v10_enable_debug_trap(struct amdgpu_device *adev, 
uint32_t kgd_gfx_v10_disable_debug_trap(struct amdgpu_device *adev,

					bool keep_trap_enabled,

					uint32_t vmid);

void kgd_gfx_v10_get_iq_wait_times(struct amdgpu_device *adev, uint32_t *wait_times);

void kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev,

					       uint32_t wait_times,

					       uint32_t grace_period,

					       uint32_t *reg_offset,

					       uint32_t *reg_data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

+2 −0
Original line number Diff line number Diff line
@@ -672,6 +672,8 @@ const struct kfd2kgd_calls gfx_v10_3_kfd2kgd = { 
	.get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info_v10_3,

	.set_vm_context_page_table_base = set_vm_context_page_table_base_v10_3,

	.program_trap_handler_settings = program_trap_handler_settings_v10_3,

	.get_iq_wait_times = kgd_gfx_v10_get_iq_wait_times,

	.build_grace_period_packet_info = kgd_gfx_v10_build_grace_period_packet_info,

	.enable_debug_trap = kgd_gfx_v10_enable_debug_trap,

	.disable_debug_trap = kgd_gfx_v10_disable_debug_trap

};