Commit 7cdda699 authored by Arnaldo Carvalho de Melo's avatar Arnaldo Carvalho de Melo
Browse files

Merge remote-tracking branch 'acme/perf-tools' into perf-tools-next 



To pick up fixes that were already merged upstream.

Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parents a9650b7f 4e111f0c

tools/arch/x86/include/asm/cpufeatures.h

+21 −5
Original line number Diff line number Diff line
@@ -97,7 +97,7 @@ 
#define X86_FEATURE_SYSENTER32		( 3*32+15) /* "" sysenter in IA32 userspace */

#define X86_FEATURE_REP_GOOD		( 3*32+16) /* REP microcode works well */

#define X86_FEATURE_AMD_LBR_V2		( 3*32+17) /* AMD Last Branch Record Extension Version 2 */

#define X86_FEATURE_LFENCE_RDTSC	( 3*32+18) /* "" LFENCE synchronizes RDTSC */

/* FREE, was #define X86_FEATURE_LFENCE_RDTSC		( 3*32+18) "" LFENCE synchronizes RDTSC */

#define X86_FEATURE_ACC_POWER		( 3*32+19) /* AMD Accumulated Power Mechanism */

#define X86_FEATURE_NOPL		( 3*32+20) /* The NOPL (0F 1F) instructions */

#define X86_FEATURE_ALWAYS		( 3*32+21) /* "" Always-present feature */
@@ -226,10 +226,9 @@ 


/* Virtualization flags: Linux defined, word 8 */

#define X86_FEATURE_TPR_SHADOW		( 8*32+ 0) /* Intel TPR Shadow */

#define X86_FEATURE_VNMI		( 8*32+ 1) /* Intel Virtual NMI */

#define X86_FEATURE_FLEXPRIORITY	( 8*32+ 2) /* Intel FlexPriority */

#define X86_FEATURE_EPT			( 8*32+ 3) /* Intel Extended Page Table */

#define X86_FEATURE_VPID		( 8*32+ 4) /* Intel Virtual Processor ID */

#define X86_FEATURE_FLEXPRIORITY	( 8*32+ 1) /* Intel FlexPriority */

#define X86_FEATURE_EPT			( 8*32+ 2) /* Intel Extended Page Table */

#define X86_FEATURE_VPID		( 8*32+ 3) /* Intel Virtual Processor ID */



#define X86_FEATURE_VMMCALL		( 8*32+15) /* Prefer VMMCALL to VMCALL */

#define X86_FEATURE_XENPV		( 8*32+16) /* "" Xen paravirtual guest */
@@ -307,14 +306,21 @@ 
#define X86_FEATURE_SGX_EDECCSSA	(11*32+18) /* "" SGX EDECCSSA user leaf function */

#define X86_FEATURE_CALL_DEPTH		(11*32+19) /* "" Call depth tracking for RSB stuffing */

#define X86_FEATURE_MSR_TSX_CTRL	(11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */

#define X86_FEATURE_SMBA		(11*32+21) /* "" Slow Memory Bandwidth Allocation */

#define X86_FEATURE_BMEC		(11*32+22) /* "" Bandwidth Monitoring Event Configuration */



/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */

#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */

#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */

#define X86_FEATURE_CMPCCXADD           (12*32+ 7) /* "" CMPccXADD instructions */

#define X86_FEATURE_ARCH_PERFMON_EXT	(12*32+ 8) /* "" Intel Architectural PerfMon Extension */

#define X86_FEATURE_FZRM		(12*32+10) /* "" Fast zero-length REP MOVSB */

#define X86_FEATURE_FSRS		(12*32+11) /* "" Fast short REP STOSB */

#define X86_FEATURE_FSRC		(12*32+12) /* "" Fast short REP {CMPSB,SCASB} */

#define X86_FEATURE_LKGS		(12*32+18) /* "" Load "kernel" (userspace) GS */

#define X86_FEATURE_AMX_FP16		(12*32+21) /* "" AMX fp16 Support */

#define X86_FEATURE_AVX_IFMA            (12*32+23) /* "" Support for VPMADD52[H,L]UQ */

#define X86_FEATURE_LAM			(12*32+26) /* Linear Address Masking */



/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */

#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
@@ -331,6 +337,7 @@ 
#define X86_FEATURE_VIRT_SSBD		(13*32+25) /* Virtualized Speculative Store Bypass Disable */

#define X86_FEATURE_AMD_SSB_NO		(13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */

#define X86_FEATURE_CPPC		(13*32+27) /* Collaborative Processor Performance Control */

#define X86_FEATURE_AMD_PSFD            (13*32+28) /* "" Predictive Store Forwarding Disable */

#define X86_FEATURE_BTC_NO		(13*32+29) /* "" Not vulnerable to Branch Type Confusion */

#define X86_FEATURE_BRS			(13*32+31) /* Branch Sampling available */
@@ -363,6 +370,7 @@ 
#define X86_FEATURE_VGIF		(15*32+16) /* Virtual GIF */

#define X86_FEATURE_X2AVIC		(15*32+18) /* Virtual x2apic */

#define X86_FEATURE_V_SPEC_CTRL		(15*32+20) /* Virtual SPEC_CTRL */

#define X86_FEATURE_VNMI		(15*32+25) /* Virtual NMI */

#define X86_FEATURE_SVME_ADDR_CHK	(15*32+28) /* "" SVME addr check */



/* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
@@ -427,6 +435,13 @@ 
#define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* "" Virtual TSC_AUX */

#define X86_FEATURE_SME_COHERENT	(19*32+10) /* "" AMD hardware-enforced cache coherency */



/* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */

#define X86_FEATURE_NO_NESTED_DATA_BP	(20*32+ 0) /* "" No Nested Data Breakpoints */

#define X86_FEATURE_LFENCE_RDTSC	(20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */

#define X86_FEATURE_NULL_SEL_CLR_BASE	(20*32+ 6) /* "" Null Selector Clears Base */

#define X86_FEATURE_AUTOIBRS		(20*32+ 8) /* "" Automatic IBRS */

#define X86_FEATURE_NO_SMM_CTL_MSR	(20*32+ 9) /* "" SMM_CTL MSR is not present */



/*

 * BUG word(s)

 */
@@ -467,5 +482,6 @@ 
#define X86_BUG_MMIO_UNKNOWN		X86_BUG(26) /* CPU is too old and its MMIO Stale Data status is unknown */

#define X86_BUG_RETBLEED		X86_BUG(27) /* CPU is affected by RETBleed */

#define X86_BUG_EIBRS_PBRSB		X86_BUG(28) /* EIBRS is vulnerable to Post Barrier RSB Predictions */

#define X86_BUG_SMT_RSB			X86_BUG(29) /* CPU is vulnerable to Cross-Thread Return Address Predictions */



#endif /* _ASM_X86_CPUFEATURES_H */

tools/arch/x86/include/asm/disabled-features.h

+7 −1
Original line number Diff line number Diff line
@@ -75,6 +75,12 @@ 
# define DISABLE_CALL_DEPTH_TRACKING	(1 << (X86_FEATURE_CALL_DEPTH & 31))

#endif



#ifdef CONFIG_ADDRESS_MASKING

# define DISABLE_LAM		0

#else

# define DISABLE_LAM		(1 << (X86_FEATURE_LAM & 31))

#endif



#ifdef CONFIG_INTEL_IOMMU_SVM

# define DISABLE_ENQCMD		0

#else
@@ -115,7 +121,7 @@ 
#define DISABLED_MASK10	0

#define DISABLED_MASK11	(DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET| \

			 DISABLE_CALL_DEPTH_TRACKING)

#define DISABLED_MASK12	0

#define DISABLED_MASK12	(DISABLE_LAM)

#define DISABLED_MASK13	0

#define DISABLED_MASK14	0

#define DISABLED_MASK15	0

tools/arch/x86/include/uapi/asm/prctl.h

+8 −0
Original line number Diff line number Diff line
@@ -16,8 +16,16 @@ 
#define ARCH_GET_XCOMP_GUEST_PERM	0x1024

#define ARCH_REQ_XCOMP_GUEST_PERM	0x1025



#define ARCH_XCOMP_TILECFG		17

#define ARCH_XCOMP_TILEDATA		18



#define ARCH_MAP_VDSO_X32		0x2001

#define ARCH_MAP_VDSO_32		0x2002

#define ARCH_MAP_VDSO_64		0x2003



#define ARCH_GET_UNTAG_MASK		0x4001

#define ARCH_ENABLE_TAGGED_ADDR		0x4002

#define ARCH_GET_MAX_TAG_BITS		0x4003

#define ARCH_FORCE_TAGGED_SVA		0x4004



#endif /* _ASM_X86_PRCTL_H */

tools/arch/x86/include/uapi/asm/unistd_32.h

+3 −0
Original line number Diff line number Diff line
@@ -2,6 +2,9 @@ 
#ifndef __NR_fork

#define __NR_fork 2

#endif

#ifndef __NR_execve

#define __NR_execve 11

#endif

#ifndef __NR_getppid

#define __NR_getppid 64

#endif

tools/arch/x86/lib/memcpy_64.S

+10 −24
Original line number Diff line number Diff line
@@ -9,13 +9,6 @@ 


.section .noinstr.text, "ax"



/*

 * We build a jump to memcpy_orig by default which gets NOPped out on

 * the majority of x86 CPUs which set REP_GOOD. In addition, CPUs which

 * have the enhanced REP MOVSB/STOSB feature (ERMS), change those NOPs

 * to a jmp to memcpy_erms which does the REP; MOVSB mem copy.

 */



/*

 * memcpy - Copy a memory block.

 *
@@ -26,17 +19,21 @@ 
 *

 * Output:

 * rax original destination

 *

 * The FSRM alternative should be done inline (avoiding the call and

 * the disgusting return handling), but that would require some help

 * from the compiler for better calling conventions.

 *

 * The 'rep movsb' itself is small enough to replace the call, but the

 * two register moves blow up the code. And one of them is "needed"

 * only for the return value that is the same as the source input,

 * which the compiler could/should do much better anyway.

 */

SYM_TYPED_FUNC_START(__memcpy)

	ALTERNATIVE_2 "jmp memcpy_orig", "", X86_FEATURE_REP_GOOD, \

		      "jmp memcpy_erms", X86_FEATURE_ERMS

	ALTERNATIVE "jmp memcpy_orig", "", X86_FEATURE_FSRM



	movq %rdi, %rax

	movq %rdx, %rcx

	shrq $3, %rcx

	andl $7, %edx

	rep movsq

	movl %edx, %ecx

	rep movsb

	RET

SYM_FUNC_END(__memcpy)
@@ -45,17 +42,6 @@ EXPORT_SYMBOL(__memcpy) 
SYM_FUNC_ALIAS(memcpy, __memcpy)

EXPORT_SYMBOL(memcpy)



/*

 * memcpy_erms() - enhanced fast string memcpy. This is faster and

 * simpler than memcpy. Use memcpy_erms when possible.

 */

SYM_FUNC_START_LOCAL(memcpy_erms)

	movq %rdi, %rax

	movq %rdx, %rcx

	rep movsb

	RET

SYM_FUNC_END(memcpy_erms)



SYM_FUNC_START_LOCAL(memcpy_orig)

	movq %rdi, %rax