Loading drivers/watchdog/pnx4008_wdt.c +11 −12 Original line number Diff line number Diff line Loading @@ -95,22 +95,21 @@ static void wdt_enable(void) spin_lock(&io_lock); /* stop counter, initiate counter reset */ __raw_writel(RESET_COUNT, WDTIM_CTRL(wdt_base)); writel(RESET_COUNT, WDTIM_CTRL(wdt_base)); /*wait for reset to complete. 100% guarantee event */ while (__raw_readl(WDTIM_COUNTER(wdt_base))) while (readl(WDTIM_COUNTER(wdt_base))) cpu_relax(); /* internal and external reset, stop after that */ __raw_writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base)); writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base)); /* configure match output */ __raw_writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base)); writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base)); /* clear interrupt, just in case */ __raw_writel(MATCH_INT, WDTIM_INT(wdt_base)); writel(MATCH_INT, WDTIM_INT(wdt_base)); /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */ __raw_writel(0xFFFF, WDTIM_PULSE(wdt_base)); __raw_writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); writel(0xFFFF, WDTIM_PULSE(wdt_base)); writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); /*enable counter, stop when debugger active */ __raw_writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base)); writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base)); spin_unlock(&io_lock); } Loading @@ -119,7 +118,7 @@ static void wdt_disable(void) { spin_lock(&io_lock); __raw_writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */ writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */ spin_unlock(&io_lock); } Loading Loading @@ -269,8 +268,8 @@ static int __devinit pnx4008_wdt_probe(struct platform_device *pdev) if (ret) goto out; boot_status = (__raw_readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ? WDIOF_CARDRESET : 0; boot_status = (readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ? WDIOF_CARDRESET : 0; wdt_disable(); /*disable for now */ clk_disable(wdt_clk); Loading Loading
drivers/watchdog/pnx4008_wdt.c +11 −12 Original line number Diff line number Diff line Loading @@ -95,22 +95,21 @@ static void wdt_enable(void) spin_lock(&io_lock); /* stop counter, initiate counter reset */ __raw_writel(RESET_COUNT, WDTIM_CTRL(wdt_base)); writel(RESET_COUNT, WDTIM_CTRL(wdt_base)); /*wait for reset to complete. 100% guarantee event */ while (__raw_readl(WDTIM_COUNTER(wdt_base))) while (readl(WDTIM_COUNTER(wdt_base))) cpu_relax(); /* internal and external reset, stop after that */ __raw_writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base)); writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base)); /* configure match output */ __raw_writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base)); writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base)); /* clear interrupt, just in case */ __raw_writel(MATCH_INT, WDTIM_INT(wdt_base)); writel(MATCH_INT, WDTIM_INT(wdt_base)); /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */ __raw_writel(0xFFFF, WDTIM_PULSE(wdt_base)); __raw_writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); writel(0xFFFF, WDTIM_PULSE(wdt_base)); writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); /*enable counter, stop when debugger active */ __raw_writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base)); writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base)); spin_unlock(&io_lock); } Loading @@ -119,7 +118,7 @@ static void wdt_disable(void) { spin_lock(&io_lock); __raw_writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */ writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */ spin_unlock(&io_lock); } Loading Loading @@ -269,8 +268,8 @@ static int __devinit pnx4008_wdt_probe(struct platform_device *pdev) if (ret) goto out; boot_status = (__raw_readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ? WDIOF_CARDRESET : 0; boot_status = (readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ? WDIOF_CARDRESET : 0; wdt_disable(); /*disable for now */ clk_disable(wdt_clk); Loading