Commit 7a28bee0 authored by Jake Wang's avatar Jake Wang Committed by Alex Deucher
Browse files

drm/amd/display: Disable dpp root clock when not being used 



[Why & How]
Disable root clock for dpp when not being used.

Reviewed-by: default avatarEric Yang <eric.yang2@amd.com>
Acked-by: default avatarAgustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: default avatarJake Wang <haonan.wang2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 652de07a

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

+4 −1
Original line number Diff line number Diff line
@@ -219,14 +219,17 @@ static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, 
		update_dispclk = true;

	}



	/* TODO: add back DTO programming when DPPCLK restore is fixed in FSDL*/

	if (dpp_clock_lowered) {

		// increase per DPP DTO before lowering global dppclk

		dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

		dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

	} else {

		// increase global DPPCLK before lowering per DPP DTO

		if (update_dppclk || update_dispclk)

			dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

		// always update dtos unless clock is lowered and not safe to lower

		if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)

			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

	}



	// notify DMCUB of latest clocks

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c

+40 −1
Original line number Diff line number Diff line
@@ -42,6 +42,45 @@ 
#define DC_LOGGER \

	dccg->ctx->logger



static void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	if (dccg->ref_dppclk && req_dppclk) {

		int ref_dppclk = dccg->ref_dppclk;

		int modulo, phase;



		// phase / modulo = dpp pipe clk / dpp global clk

		modulo = 0xff;   // use FF at the end

		phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;



		if (phase > 0xff) {

			ASSERT(false);

			phase = 0xff;

		}



		REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,

				DPPCLK0_DTO_PHASE, phase,

				DPPCLK0_DTO_MODULO, modulo);

		REG_UPDATE(DPPCLK_DTO_CTRL,

				DPPCLK_DTO_ENABLE[dpp_inst], 1);

	} else {

		//DTO must be enabled to generate a 0Hz clock output

		if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) {

			REG_UPDATE(DPPCLK_DTO_CTRL,

					DPPCLK_DTO_ENABLE[dpp_inst], 1);

			REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,

					DPPCLK0_DTO_PHASE, 0,

					DPPCLK0_DTO_MODULO, 1);

		} else {

			REG_UPDATE(DPPCLK_DTO_CTRL,

					DPPCLK_DTO_ENABLE[dpp_inst], 0);

		}

	}

	dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

}





void dccg31_set_dpstreamclk(

		struct dccg *dccg,

		enum hdmistreamclk_source src,
@@ -401,7 +440,7 @@ void dccg31_init(struct dccg *dccg) 
}



static const struct dccg_funcs dccg31_funcs = {

	.update_dpp_dto = dccg2_update_dpp_dto,

	.update_dpp_dto = dccg31_update_dpp_dto,

	.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,

	.dccg_init = dccg31_init,

	.set_dpstreamclk = dccg31_set_dpstreamclk,