Commit 796f0ae8 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v5.13-next-dts64' of... 

Merge tag 'v5.13-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

mt8173:
- split hardware encoder block into two devices.

mt8167:
- add pm domains, multi-media system (mmsys), SMI, local arbiter
  (larb) and IOMMU nodes.

mt8183:
- Add new chromebooks: HP Chromebook 11a, Acer Chromebook 311, HP
  Chromebook x360 11MK G3 EE, Lenovo IdeaPad Flex 3.
- add power domain to SMI common node.
- add power supplies for EEPROM node.

* tag 'v5.13-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (21 commits)
  arm64: dts: mt8183: Add node for the Mali GPU
  arm64: dts: mt8183-kukui: Add tboard thermal zones
  arm64: dts: mt8183: add cbas node under cros_ec
  arm64: dts: mt8183: add supply name for eeprom
  arm64: dts: mt8183: remove syscon from smi_common node
  arm64: dts: mt8183: Add kukui-jacuzzi-fennel board
  arm64: dts: mt8183: Add kukui-jacuzzi-kenzo board
  arm64: dts: mt8183: Add kukui-jacuzzi-burnet board
  arm64: dts: mt8183: Add kukui-jacuzzi-willow board
  arm64: dts: mt8183: Add kukui-jacuzzi-kappa board
  dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-fennel
  dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-kenzo
  dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-burnet
  dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-willow
  dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-kappa
  arm64: dts: mediatek: mt8167: add iommu node
  arm64: dts: mediatek: mt8167: add larb nodes
  arm64: dts: mediatek: mt8167: add smi_common node
  arm64: dts: mediatek: mt8167: add mmsys node
  arm64: dts: mediatek: mt8167: add power domains
  ...

Link: https://lore.kernel.org/r/117d5eb5-bc99-70bb-a1a9-d7141fe96527@gmail.com


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents a3c52f08 a8168ceb

Documentation/devicetree/bindings/arm/mediatek.yaml

+27 −2
Original line number Diff line number Diff line
@@ -122,6 +122,10 @@ properties: 
          - enum:

              - mediatek,mt8195-evb

          - const: mediatek,mt8195

      - description: Google Burnet (HP Chromebook x360 11MK G3 EE)

        items:

          - const: google,burnet

          - const: mediatek,mt8183

      - description: Google Krane (Lenovo IdeaPad Duet, 10e,...)

        items:

          - enum:
@@ -133,9 +137,19 @@ properties: 
        items:

          - const: google,damu

          - const: mediatek,mt8183

      - description: Google Juniper (Acer Chromebook Spin 311)

      - description: Google Fennel (Lenovo IdeaPad 3 Chromebook)

        items:

          - enum:

              - google,fennel-sku0

              - google,fennel-sku1

              - google,fennel-sku6

          - const: google,fennel

          - const: mediatek,mt8183

      - description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311)

        items:

          - const: google,juniper-sku16

          - enum:

              - google,juniper-sku16

              - google,juniper-sku17

          - const: google,juniper

          - const: mediatek,mt8183

      - description: Google Kakadu (ASUS Chromebook Detachable CM3)
@@ -144,6 +158,10 @@ properties: 
          - const: google,kakadu-rev2

          - const: google,kakadu

          - const: mediatek,mt8183

      - description: Google Kappa (HP Chromebook 11a)

        items:

          - const: google,kappa

          - const: mediatek,mt8183

      - description: Google Kodama (Lenovo 10e Chromebook Tablet)

        items:

          - enum:
@@ -153,6 +171,13 @@ properties: 
              - google,kodama-sku32

          - const: google,kodama

          - const: mediatek,mt8183

      - description: Google Willow (Acer Chromebook 311 C722/C722T)

        items:

          - enum:

              - google,willow-sku0

              - google,willow-sku1

          - const: google,willow

          - const: mediatek,mt8183

      - items:

          - enum:

              - mediatek,mt8183-pumpkin

arch/arm64/boot/dts/mediatek/Makefile

+8 −0
Original line number Diff line number Diff line
@@ -13,8 +13,16 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb 
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb

arch/arm64/boot/dts/mediatek/mt8167.dtsi

+121 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 


#include <dt-bindings/clock/mt8167-clk.h>

#include <dt-bindings/memory/mt8167-larb-port.h>

#include <dt-bindings/power/mt8167-power.h>



#include "mt8167-pinfunc.h"
@@ -34,6 +35,73 @@ apmixedsys: apmixedsys@10018000 { 
			#clock-cells = <1>;

		};



		scpsys: syscon@10006000 {

			compatible = "syscon", "simple-mfd";

			reg = <0 0x10006000 0 0x1000>;

			#power-domain-cells = <1>;



			spm: power-controller {

				compatible = "mediatek,mt8167-power-controller";

				#address-cells = <1>;

				#size-cells = <0>;

				#power-domain-cells = <1>;



				/* power domains of the SoC */

				power-domain@MT8167_POWER_DOMAIN_MM {

					reg = <MT8167_POWER_DOMAIN_MM>;

					clocks = <&topckgen CLK_TOP_SMI_MM>;

					clock-names = "mm";

					#power-domain-cells = <0>;

					mediatek,infracfg = <&infracfg>;

				};



				power-domain@MT8167_POWER_DOMAIN_VDEC {

					reg = <MT8167_POWER_DOMAIN_VDEC>;

					clocks = <&topckgen CLK_TOP_SMI_MM>,

						 <&topckgen CLK_TOP_RG_VDEC>;

					clock-names = "mm", "vdec";

					#power-domain-cells = <0>;

				};



				power-domain@MT8167_POWER_DOMAIN_ISP {

					reg = <MT8167_POWER_DOMAIN_ISP>;

					clocks = <&topckgen CLK_TOP_SMI_MM>;

					clock-names = "mm";

					#power-domain-cells = <0>;

				};



				power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {

					reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>;

					clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,

						 <&topckgen CLK_TOP_RG_SLOW_MFG>;

					clock-names = "axi_mfg", "mfg";

					#address-cells = <1>;

					#size-cells = <0>;

					#power-domain-cells = <1>;

					mediatek,infracfg = <&infracfg>;



					power-domain@MT8167_POWER_DOMAIN_MFG_2D {

						reg = <MT8167_POWER_DOMAIN_MFG_2D>;

						#address-cells = <1>;

						#size-cells = <0>;

						#power-domain-cells = <1>;



						power-domain@MT8167_POWER_DOMAIN_MFG {

							reg = <MT8167_POWER_DOMAIN_MFG>;

							#power-domain-cells = <0>;

							mediatek,infracfg = <&infracfg>;

						};

					};

				};



				power-domain@MT8167_POWER_DOMAIN_CONN {

					reg = <MT8167_POWER_DOMAIN_CONN>;

					#power-domain-cells = <0>;

					mediatek,infracfg = <&infracfg>;

				};

			};

		};



		imgsys: syscon@15000000 {

			compatible = "mediatek,mt8167-imgsys", "syscon";

			reg = <0 0x15000000 0 0x1000>;
@@ -57,5 +125,58 @@ pio: pinctrl@1000b000 { 
			#interrupt-cells = <2>;

			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;

		};



		mmsys: mmsys@14000000 {

			compatible = "mediatek,mt8167-mmsys", "syscon";

			reg = <0 0x14000000 0 0x1000>;

			#clock-cells = <1>;

		};



		smi_common: smi@14017000 {

			compatible = "mediatek,mt8167-smi-common";

			reg = <0 0x14017000 0 0x1000>;

			clocks = <&mmsys CLK_MM_SMI_COMMON>,

				 <&mmsys CLK_MM_SMI_COMMON>;

			clock-names = "apb", "smi";

			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;

		};



		larb0: larb@14016000 {

			compatible = "mediatek,mt8167-smi-larb";

			reg = <0 0x14016000 0 0x1000>;

			mediatek,smi = <&smi_common>;

			clocks = <&mmsys CLK_MM_SMI_LARB0>,

				 <&mmsys CLK_MM_SMI_LARB0>;

			clock-names = "apb", "smi";

			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;

		};



		larb1: larb@15001000 {

			compatible = "mediatek,mt8167-smi-larb";

			reg = <0 0x15001000 0 0x1000>;

			mediatek,smi = <&smi_common>;

			clocks = <&imgsys CLK_IMG_LARB1_SMI>,

				 <&imgsys CLK_IMG_LARB1_SMI>;

			clock-names = "apb", "smi";

			power-domains = <&spm MT8167_POWER_DOMAIN_ISP>;

		};



		larb2: larb@16010000 {

			compatible = "mediatek,mt8167-smi-larb";

			reg = <0 0x16010000 0 0x1000>;

			mediatek,smi = <&smi_common>;

			clocks = <&vdecsys CLK_VDEC_CKEN>,

				 <&vdecsys CLK_VDEC_LARB1_CKEN>;

			clock-names = "apb", "smi";

			power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;

		};



		iommu: m4u@10203000 {

			compatible = "mediatek,mt8167-m4u";

			reg = <0 0x10203000 0 0x1000>;

			mediatek,larbs = <&larb0 &larb1 &larb2>;

			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;

			#iommu-cells = <1>;

		};

	};

};

arch/arm64/boot/dts/mediatek/mt8173.dtsi

+31 −29
Original line number Diff line number Diff line
@@ -1459,14 +1459,11 @@ larb3: larb@18001000 { 
			clock-names = "apb", "smi";

		};



		vcodec_enc: vcodec@18002000 {

		vcodec_enc_avc: vcodec@18002000 {

			compatible = "mediatek,mt8173-vcodec-enc";

			reg = <0 0x18002000 0 0x1000>,	/* VENC_SYS */

			      <0 0x19002000 0 0x1000>;	/* VENC_LT_SYS */

			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,

				     <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;

			mediatek,larb = <&larb3>,

					<&larb5>;

			reg = <0 0x18002000 0 0x1000>;	/* VENC_SYS */

			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;

			mediatek,larb = <&larb3>;

			iommus = <&iommu M4U_PORT_VENC_RCPU>,

				 <&iommu M4U_PORT_VENC_REC>,

				 <&iommu M4U_PORT_VENC_BSDMA>,
@@ -1477,29 +1474,12 @@ vcodec_enc: vcodec@18002000 { 
				 <&iommu M4U_PORT_VENC_REF_LUMA>,

				 <&iommu M4U_PORT_VENC_REF_CHROMA>,

				 <&iommu M4U_PORT_VENC_NBM_RDMA>,

				 <&iommu M4U_PORT_VENC_NBM_WDMA>,

				 <&iommu M4U_PORT_VENC_RCPU_SET2>,

				 <&iommu M4U_PORT_VENC_REC_FRM_SET2>,

				 <&iommu M4U_PORT_VENC_BSDMA_SET2>,

				 <&iommu M4U_PORT_VENC_SV_COMA_SET2>,

				 <&iommu M4U_PORT_VENC_RD_COMA_SET2>,

				 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,

				 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,

				 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,

				 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;

				 <&iommu M4U_PORT_VENC_NBM_WDMA>;

			mediatek,vpu = <&vpu>;

			clocks = <&topckgen CLK_TOP_VENCPLL_D2>,

				 <&topckgen CLK_TOP_VENC_SEL>,

				 <&topckgen CLK_TOP_UNIVPLL1_D2>,

				 <&topckgen CLK_TOP_VENC_LT_SEL>;

			clock-names = "venc_sel_src",

				      "venc_sel",

				      "venc_lt_sel_src",

				      "venc_lt_sel";

			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,

					  <&topckgen CLK_TOP_VENC_LT_SEL>;

			assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>,

						 <&topckgen CLK_TOP_VCODECPLL_370P5>;

			clocks = <&topckgen CLK_TOP_VENC_SEL>;

			clock-names = "venc_sel";

			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;

			assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;

		};



		jpegdec: jpegdec@18004000 {
@@ -1531,5 +1511,27 @@ larb5: larb@19001000 { 
				 <&vencltsys CLK_VENCLT_CKE0>;

			clock-names = "apb", "smi";

		};



		vcodec_enc_vp8: vcodec@19002000 {

			compatible = "mediatek,mt8173-vcodec-enc-vp8";

			reg =  <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */

			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;

			iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,

				 <&iommu M4U_PORT_VENC_REC_FRM_SET2>,

				 <&iommu M4U_PORT_VENC_BSDMA_SET2>,

				 <&iommu M4U_PORT_VENC_SV_COMA_SET2>,

				 <&iommu M4U_PORT_VENC_RD_COMA_SET2>,

				 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,

				 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,

				 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,

				 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;

			mediatek,larb = <&larb5>;

			mediatek,vpu = <&vpu>;

			clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;

			clock-names = "venc_lt_sel";

			assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;

			assigned-clock-parents =

				 <&topckgen CLK_TOP_VCODECPLL_370P5>;

		};

	};

};

arch/arm64/boot/dts/mediatek/mt8183-evb.dts

+5 −0
Original line number Diff line number Diff line
@@ -42,6 +42,11 @@ &auxadc { 
	status = "okay";

};



&gpu {

	mali-supply = <&mt6358_vgpu_reg>;

	sram-supply = <&mt6358_vsram_gpu_reg>;

};



&i2c0 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c_pins_0>;