Commit 78af3cc6 authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo
Browse files

rtw89: 8852c: add basic and remaining chip_info 



The chip_info include BT coexistence tables, size and number of hardware
components, and supported functions.

Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220503120001.79272-4-pkshih@realtek.com
parent e212d5d4

drivers/net/wireless/realtek/rtw89/rtw8852c.c

+77 −3
Original line number Diff line number Diff line
@@ -2662,6 +2662,48 @@ s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 
	return clamp_t(s8, val, -100, 0) + 100;

}



static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_ul[] = {

	{255, 0, 0, 7}, /* 0 -> original */

	{255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */

	{255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */

	{255, 0, 0, 7}, /* 3- >reserved for shared-antenna */

	{255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */

	{255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */

	{6, 1, 0, 7},

	{13, 1, 0, 7},

	{13, 1, 0, 7}

};



static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_dl[] = {

	{255, 0, 0, 7}, /* 0 -> original */

	{255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */

	{255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */

	{255, 0, 0, 7}, /* 3- >reserved for shared-antenna */

	{255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */

	{255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */

	{255, 1, 0, 7},

	{255, 1, 0, 7},

	{255, 1, 0, 7}

};



static const u8 rtw89_btc_8852c_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};

static const u8 rtw89_btc_8852c_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28};



static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852c_mon_reg[] = {

	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda00),

	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda04),

	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),

	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),

	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),

	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda38),

	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda44),

	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda48),

	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),

	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),

	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),

	RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),

};



static

void rtw8852c_btc_bt_aci_imp(struct rtw89_dev *rtwdev)

{
@@ -2795,10 +2837,13 @@ static const struct rtw89_chip_ops rtw8852c_chip_ops = { 
	.disable_bb_rf		= rtw8852c_mac_disable_bb_rf,

	.bb_reset		= rtw8852c_bb_reset,

	.bb_sethw		= rtw8852c_bb_sethw,

	.read_rf		= rtw89_phy_read_rf_v1,

	.write_rf		= rtw89_phy_write_rf_v1,

	.set_channel		= rtw8852c_set_channel,

	.set_channel_help	= rtw8852c_set_channel_help,

	.read_efuse		= rtw8852c_read_efuse,

	.read_phycap		= rtw8852c_read_phycap,

	.fem_setup		= NULL,

	.rfk_init		= rtw8852c_rfk_init,

	.rfk_channel		= rtw8852c_rfk_channel,

	.rfk_band_changed	= rtw8852c_rfk_band_changed,
@@ -2809,12 +2854,11 @@ static const struct rtw89_chip_ops rtw8852c_chip_ops = { 
	.set_txpwr_ctrl		= rtw8852c_set_txpwr_ctrl,

	.init_txpwr_unit	= rtw8852c_init_txpwr_unit,

	.get_thermal		= rtw8852c_get_thermal,

	.ctrl_btg		= rtw8852c_ctrl_btg,

	.query_ppdu		= rtw8852c_query_ppdu,

	.bb_ctrl_btc_preagc	= rtw8852c_bb_ctrl_btc_preagc,

	.read_rf		= rtw89_phy_read_rf_v1,

	.write_rf		= rtw89_phy_write_rf_v1,

	.set_txpwr_ul_tb_offset	= rtw8852c_set_txpwr_ul_tb_offset,

	.cfg_txrx_path		= rtw8852c_bb_cfg_txrx_path,

	.set_txpwr_ul_tb_offset	= rtw8852c_set_txpwr_ul_tb_offset,

	.pwr_on_func		= rtw8852c_pwr_on_func,

	.pwr_off_func		= rtw8852c_pwr_off_func,

	.fill_txdesc		= rtw89_core_fill_txdesc_v1,
@@ -2839,6 +2883,10 @@ const struct rtw89_chip_info rtw8852c_chip_info = { 
	.chip_id		= RTL8852C,

	.ops			= &rtw8852c_chip_ops,

	.fw_name		= "rtw89/rtw8852c_fw.bin",

	.fifo_size		= 458752,

	.max_amsdu_limit	= 8000,

	.dis_2g_40m_ul_ofdma	= false,

	.rsvd_ple_ofst		= 0x6f800,

	.hfc_param_ini		= rtw8852c_hfc_param_ini_pcie,

	.dle_mem		= rtw8852c_dle_mem_pcie,

	.rf_base_addr		= {0xe000, 0xf000},
@@ -2860,7 +2908,17 @@ const struct rtw89_chip_info rtw8852c_chip_info = { 
	.txpwr_factor_mac	= 1,

	.dig_table		= NULL,

	.tssi_dbw_table		= &rtw89_8852c_tssi_dbw_table,

	.support_bands		= BIT(NL80211_BAND_2GHZ) |

				  BIT(NL80211_BAND_5GHZ) |

				  BIT(NL80211_BAND_6GHZ),

	.support_bw160		= true,

	.hw_sec_hdr		= true,

	.rf_path_num		= 2,

	.tx_nss			= 2,

	.rx_nss			= 2,

	.acam_num		= 128,

	.bcam_num		= 20,

	.scam_num		= 128,

	.sec_ctrl_efuse_size	= 4,

	.physical_efuse_size	= 1216,

	.logical_efuse_size	= 2048,
@@ -2869,6 +2927,22 @@ const struct rtw89_chip_info rtw8852c_chip_info = { 
	.dav_log_efuse_size	= 16,

	.phycap_addr		= 0x590,

	.phycap_size		= 0x60,

	.para_ver		= 0x05050764,

	.wlcx_desired		= 0x05050000,

	.btcx_desired		= 0x5,

	.scbd			= 0x1,

	.mailbox		= 0x1,

	.afh_guard_ch		= 6,

	.wl_rssi_thres		= rtw89_btc_8852c_wl_rssi_thres,

	.bt_rssi_thres		= rtw89_btc_8852c_bt_rssi_thres,

	.rssi_tol		= 2,

	.mon_reg_num		= ARRAY_SIZE(rtw89_btc_8852c_mon_reg),

	.mon_reg		= rtw89_btc_8852c_mon_reg,

	.rf_para_ulink_num	= ARRAY_SIZE(rtw89_btc_8852c_rf_ul),

	.rf_para_ulink		= rtw89_btc_8852c_rf_ul,

	.rf_para_dlink_num	= ARRAY_SIZE(rtw89_btc_8852c_rf_dl),

	.rf_para_dlink		= rtw89_btc_8852c_rf_dl,

	.ps_mode_supported	= 0,

	.low_power_hci_modes	= BIT(RTW89_PS_MODE_CLK_GATED) |

				  BIT(RTW89_PS_MODE_PWR_GATED),

	.h2c_cctl_func_id	= H2C_FUNC_MAC_CCTLINFO_UD_V1,