Commit 778f8e6a authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: drop unnecessary wrapper around pcie parameters setting



This can also help to maintain clear code layer.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 42f75c84
Loading
Loading
Loading
Loading
+31 −2
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@
#include "navi10_ppt.h"
#include "sienna_cichlid_ppt.h"
#include "renoir_ppt.h"
#include "amd_pcie.h"

/*
 * DO NOT use these for err/warn/info/debug messages.
@@ -993,6 +994,7 @@ static int smu_sw_fini(void *handle)
static int smu_smc_hw_setup(struct smu_context *smu)
{
	struct amdgpu_device *adev = smu->adev;
	uint32_t pcie_gen = 0, pcie_width = 0;
	int ret;

	if (smu_is_dpm_running(smu) && adev->in_suspend) {
@@ -1062,9 +1064,36 @@ static int smu_smc_hw_setup(struct smu_context *smu)
	if (!smu_is_dpm_running(smu))
		dev_info(adev->dev, "dpm has been disabled\n");

	ret = smu_override_pcie_parameters(smu);
	if (ret)
	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
		pcie_gen = 3;
	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
		pcie_gen = 2;
	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
		pcie_gen = 1;
	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
		pcie_gen = 0;

	/* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
	 * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
	 * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
	 */
	if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
		pcie_width = 6;
	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
		pcie_width = 5;
	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
		pcie_width = 4;
	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
		pcie_width = 3;
	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
		pcie_width = 2;
	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
		pcie_width = 1;
	ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
	if (ret) {
		dev_err(adev->dev, "Attempt to override pcie params failed!\n");
		return ret;
	}

	ret = smu_enable_thermal_alert(smu);
	if (ret) {
+0 −1
Original line number Diff line number Diff line
@@ -2422,7 +2422,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
	.baco_exit = smu_v11_0_baco_exit,
	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
	.override_pcie_parameters = NULL,
	.set_df_cstate = arcturus_set_df_cstate,
	.allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
	.log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
+0 −1
Original line number Diff line number Diff line
@@ -568,7 +568,6 @@ struct pptable_funcs {
	int (*mode2_reset)(struct smu_context *smu);
	int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
	int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
	int (*override_pcie_parameters)(struct smu_context *smu);
	int (*disable_umc_cdr_12gbps_workaround)(struct smu_context *smu);
	int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);
	void (*log_thermal_throttling_event)(struct smu_context *smu);
+0 −2
Original line number Diff line number Diff line
@@ -270,8 +270,6 @@ int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
					  uint32_t min,
					  uint32_t max);

int smu_v11_0_override_pcie_parameters(struct smu_context *smu);

int smu_v11_0_set_performance_level(struct smu_context *smu,
				    enum amd_dpm_forced_level level);

+0 −1
Original line number Diff line number Diff line
@@ -2435,7 +2435,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
	.baco_exit = smu_v11_0_baco_exit,
	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
	.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
	.set_default_od_settings = navi10_set_default_od_settings,
	.od_edit_dpm_table = navi10_od_edit_dpm_table,
	.run_btc = navi10_run_btc,
Loading