Commit 76411afd authored by Jack Xiao's avatar Jack Xiao Committed by Alex Deucher
Browse files

drm/amdgpu/sdma5: add mes queue fence handling 



From IH ring buffer look up the coresponding kernel queue and process.

Signed-off-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 217d29f1

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

+18 −0
Original line number Diff line number Diff line
@@ -1555,7 +1555,25 @@ static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev, 
				      struct amdgpu_irq_src *source,

				      struct amdgpu_iv_entry *entry)

{

	uint32_t mes_queue_id = entry->src_data[0];



	DRM_DEBUG("IH: SDMA trap\n");



	if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {

		struct amdgpu_mes_queue *queue;



		mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;



		spin_lock(&adev->mes.queue_id_lock);

		queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);

		if (queue) {

			DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);

			amdgpu_fence_process(queue->ring);

		}

		spin_unlock(&adev->mes.queue_id_lock);

		return 0;

	}



	switch (entry->client_id) {

	case SOC15_IH_CLIENTID_SDMA0:

		switch (entry->ring_id) {