Commit 74002e66 authored by Sascha Hauer's avatar Sascha Hauer Committed by Chanwoo Choi
Browse files

PM / devfreq: rk3399_dmc,dfi: generalize DDRTYPE defines 

The DDRTYPE defines are named to be RK3399 specific, but they can be
used for other Rockchip SoCs as well, so replace the RK3399_PMUGRF_
prefix with ROCKCHIP_. They are defined in a SoC specific header
file, so when generalizing the prefix also move the new defines to
a SoC agnostic header file. While at it use GENMASK to define the
DDRTYPE bitfield and give it a name including the full register name.

Link: https://lore.kernel.org/all/20231018061714.3553817-9-s.hauer@pengutronix.de/


Reviewed-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Acked-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
parent 63dcf38e

drivers/devfreq/event/rockchip-dfi.c

+5 −4
Original line number Diff line number Diff line
@@ -18,8 +18,10 @@ 
#include <linux/list.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/bitfield.h>

#include <linux/bits.h>



#include <soc/rockchip/rockchip_grf.h>

#include <soc/rockchip/rk3399_grf.h>



#define DMC_MAX_CHANNELS	2
@@ -75,9 +77,9 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) 
	writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);



	/* set ddr type to dfi */

	if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)

	if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)

		writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);

	else if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)

	else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)

		writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);



	/* enable count, use software mode */
@@ -192,8 +194,7 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) 


	/* get ddr type */

	regmap_read(regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);

	dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &

			RK3399_PMUGRF_DDRTYPE_MASK;

	dfi->ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val);



	dfi->channel_mask = GENMASK(1, 0);

	dfi->max_channels = 2;

drivers/devfreq/rk3399_dmc.c

+5 −5
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#include <linux/suspend.h>



#include <soc/rockchip/pm_domains.h>

#include <soc/rockchip/rockchip_grf.h>

#include <soc/rockchip/rk3399_grf.h>

#include <soc/rockchip/rockchip_sip.h>
@@ -381,17 +382,16 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev) 
	}



	regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);

	ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &

		    RK3399_PMUGRF_DDRTYPE_MASK;

	ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val);



	switch (ddr_type) {

	case RK3399_PMUGRF_DDRTYPE_DDR3:

	case ROCKCHIP_DDRTYPE_DDR3:

		data->odt_dis_freq = data->ddr3_odt_dis_freq;

		break;

	case RK3399_PMUGRF_DDRTYPE_LPDDR3:

	case ROCKCHIP_DDRTYPE_LPDDR3:

		data->odt_dis_freq = data->lpddr3_odt_dis_freq;

		break;

	case RK3399_PMUGRF_DDRTYPE_LPDDR4:

	case ROCKCHIP_DDRTYPE_LPDDR4:

		data->odt_dis_freq = data->lpddr4_odt_dis_freq;

		break;

	default:

include/soc/rockchip/rk3399_grf.h

+1 −6
Original line number Diff line number Diff line
@@ -11,11 +11,6 @@ 


/* PMU GRF Registers */

#define RK3399_PMUGRF_OS_REG2		0x308

#define RK3399_PMUGRF_DDRTYPE_SHIFT	13

#define RK3399_PMUGRF_DDRTYPE_MASK	7

#define RK3399_PMUGRF_DDRTYPE_DDR3	3

#define RK3399_PMUGRF_DDRTYPE_LPDDR2	5

#define RK3399_PMUGRF_DDRTYPE_LPDDR3	6

#define RK3399_PMUGRF_DDRTYPE_LPDDR4	7

#define RK3399_PMUGRF_OS_REG2_DDRTYPE		GENMASK(15, 13)



#endif

include/soc/rockchip/rockchip_grf.h

0 → 100644
+17 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0+ */

/*

 * Rockchip General Register Files definitions

 */



#ifndef __SOC_ROCKCHIP_GRF_H

#define __SOC_ROCKCHIP_GRF_H



/* Rockchip DDRTYPE defines */

enum {

	ROCKCHIP_DDRTYPE_DDR3	= 3,

	ROCKCHIP_DDRTYPE_LPDDR2	= 5,

	ROCKCHIP_DDRTYPE_LPDDR3	= 6,

	ROCKCHIP_DDRTYPE_LPDDR4	= 7,

};



#endif /* __SOC_ROCKCHIP_GRF_H */