Commit 73b19174 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amdgpu: Add CLK IP base offset 



so we can read/write the registers in CLK domain
through RREG32/WREG32_SOC15

Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 02374bbd

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −0
Original line number Diff line number Diff line
@@ -1398,6 +1398,7 @@ enum amd_hw_ip_block_type { 
	PWR_HWIP,

	NBIF_HWIP,

	THM_HWIP,

	CLK_HWIP,

	MAX_HWIP

};

drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ int vega10_reg_base_init(struct amdgpu_device *adev) 
		adev->reg_offset[PWR_HWIP][i] = (uint32_t *)(&(PWR_BASE.instance[i]));

		adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIF_BASE.instance[i]));

		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

		adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));

	}

	return 0;

}